參數(shù)資料
型號: MAX4919BETD+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/19頁
文件大小: 0K
描述: IC CTLR OVP/OCP BATT PWR 14-TDFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 過壓和過流控制器
應用: 手機,數(shù)碼相機,媒體播放器
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應商設備封裝: 14-TDFN-EP(3x3)
包裝: 帶卷 (TR)
Detailed Description
Undervoltage Lockout (UVLO)
The MAX4919B/MAX4920B have a 4.27V (typ) under-
voltage threshold (UVLO), while the MAX4921B has
2.35V (typ) UVLO threshold. When VIN is less than
UVLO, GN1 is held low and ACOK is high impedance.
Overvoltage Lockout Thresholds (OVLO)
The MAX4919B has a 6.38V (typ) overvoltage threshold
(OVLO), the MAX4920B has a 5.8V (typ) typical OVLO,
and the MAX4921B has a 4.65V (typ) OVLO. When VIN
is greater than OVLO, GN1 is held low and ACOK is
high impedance.
Powering the MAX4919B/
MAX4920B/MAX4921B
BTI powers the MAX4919B/MAX4920B/MAX4921B inter-
nal circuitry. BTI also connects internally to a 1.8A (min)
pFET that conducts an external load to the battery using
the BTO output. See the Battery Switchover section.
GP1 Driver
When the input voltage goes above ground, GP1 pulls
low and turns on the pFET. An internal clamp protects
the pFET by insuring that the GP1 to IN voltage does
not exceed 19.5V when the input (IN) rises to 28V.
MAX4919B/MAX4920B/MAX4921B
Battery Power-Up Logic with Overvoltage
and Overcurrent Protection
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
FUNCTION
1
GP1
p-Channel MOSFET Gate-Drive Output. GP1 pulls the external pFET gate down when the input is above
ground.
2IN
Voltage Input. IN powers the charge pump required to turn on GN1. When the correct adapter is
plugged in, a one-shot turns on the internal pFET for 1.2s, allowing time for the microprocessor (P) to
power-up and drive PWR_HOLD high. Bypass IN with a minimum 1F ceramic capacitor as close as
possible to the device for ±15kV ESD protection. When operating the
MAX4919B/MAX4920B/MAX4921B with an external pFET at GP1, place the 1F capacitor to GND as
close to the drain of the pFET as possible for the ±15kV ESD protection. If ±15kV ESD protection is not
required, place a minimum 0.1F capacitor at IN to GND.
3
GN1
n-Channel MOSFET Gate-Drive Output. GN1 is the output of an on-chip charge pump. When VUVLO <
VIN < VOVLO, GN1 is driven above the source voltage to turn on the external n-channel MOSFET.
4, 5
BTI
Battery Switch Input. BTI powers the internal circuitry. Bypass BTI with a 0.1F capacitor. Both BTI
inputs must be externally connected together.
6
HP_PWR
Car-Kit Detection Input. When a car kit is plugged into HP_PWR, a one-shot turns on the internal pFET
for 1.2s, allowing time for the P to power-up and drive PWR_HOLD high.
7
PWR_ON
Power-On Input. Drive PWR_ON high to turn on the internal pFET. The inverse of the PWR_ON logic
state is represented at the ONOK logic output.
8
GND
Ground
9
ONOK
Open-Drain PWR_ON Indicator Output. ONOK is a logic output with the inverse state of the PWR_ON
input.
10, 11
BTO
Battery Switch Output. Both BTO outputs must be externally connected together.
12
PWR_HOLD Power-Hold Input. Drive PWR_HOLD high to turn on internal pFET.
13
ACOK
Open-Drain Adapter Voltage Indicator Output. ACOK pulls low when the adapter voltage is stable
between UVLO and OVLO for 25ms. Connect a pullup resistor from ACOK to a logic supply.
14
EN
Enable Input. Drive EN low for normal operation. Drive EN high to turn off the external MOSFETs and
enter shutdown mode.
EP
Exposed Paddle. Connect EP to ground.
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