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參數(shù)資料
| 型號： | MAX3885ECB+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC 1:16 DESERIALIZER 64-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 2.5Gbps |
| 輸入類型： | PECL |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 16 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
MAX3885
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100
Ω differential
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
_______________________________________________________________________________________
5
16-BIT
SHIFT
REGISTER
16-BIT
PARALLEL
OUTPUT
REGISTER
4-BIT
COUNTER
LVDS
PECL
LVDS
PD15+
PD15-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SD+
SD-
SCLK+
SCLK-
SYNC+
SYNC-
100
Ω
MAX3885
Figure 2. Functional Diagram
SCLK
SD
SYNC
PCLK
D0
D15
D14
D13
D16
D32
D48
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D65
(LSB) PD0
D1
D17
D33
D49
D66
PD1
D15
(MSB)
TRANSMITTED FIRST
D31
D47
D64
D80
PD15
Figure 3. Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3885EVKIT | 功能描述:串行器/解串器 - Serdes Evaluation Kit for the MAX3885 RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3886ETN+ | 功能描述:串行器/解串器 - Serdes CDR w/Integrated Serial/Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3886ETN+T | 功能描述:串行器/解串器 - Serdes CDR w/Integrated Serial/Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX388C/D | 功能描述:多路器開關(guān) IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MAX388CJN | 功能描述:多路器開關(guān) IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
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