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參數(shù)資料
| 型號(hào)： | MAX3875 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 16-Channel LVDM Transceiver 64-TSSOP -40 to 85 |
| 中文描述： | 2.5Gbps、低功耗、+3.3V時(shí)鐘恢復(fù)與數(shù)據(jù)再定時(shí)IC |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 126K |
| 代理商： | MAX3875 |
M
2.5Gbps, Low-Power, +3.3V
Cloc k Rec overy and Data Retiming IC
_______________________________________________________________________________________
5
SDI+
SDI-
SLBI+
SLBI-
SCLKO-
SCLKO+
SDO+
SDO-
PHASE &
FREQUENCY
DETECTOR
PHADJ-
FIL+
FIL-
LOOP
FILTER
MAX3875
LOL
PHADJ+
SIS
MUX
AMP
AMP
CK
D
Q
VCO
I
Q
PECL
PECL
TTL
Figure 3. Functional Diagram
NAME
SCLKO+
FUNCTION
PIN
19
27
28
30
31
PHADJ -
PHADJ
+
FIL-
FIL+
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not used.
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not used.
Negative Filter Input. PLL loop filter connection. Connect a 1.0μF capacitor between FIL+ and FIL-.
Positive Filter Input. PLL loop filter connection. Connect a 1.0μF capacitor between FIL+ and FIL-.
25
LOL
Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10k
pull-up resistor)
23
SDO+
Positive Data Output, PECL compatible, 2.488Gbps
22
SDO-
Negative Data Output, PECL compatible, 2.488Gbps
Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
Pin Desc ription (c ontinued)
Detailed Desc ription
The MAX3875 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and PECL output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept a
differential input amplitude from 50mVp-p up to
800mVp-p. The bit error rate is better than 1
·
10
-10
for
input signals as small as 10mVp-p, although the jitter
tolerance performance will be degraded. For interfacing
with PECL signal levels, see Applications Information
Phase Detec tor
The phase detector incorporated in the MAX3875 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming. The
external phase adjust pins (PHADJ +, PHADJ -) allow the
user to vary the internal phase alignment.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3875AE/D | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX3875AEHJ | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX3875AEHJ-T | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX3875E/D | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX3875E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
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