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參數(shù)資料
| 型號(hào)： | MAX3872ETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/AMP 32-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.67GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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MAX3872
Setting the Loop Filter
The MAX3872 is designed for regenerator and receiver
applications. Its fully integrated PLL is a classic 2nd-order
feedback system, with a jitter transfer bandwidth (JBW)
below 2.0MHz. The external capacitor (CFIL) connected
from FIL to VCC_VCO sets the PLL loop damping. Note
that the PLL jitter transfer bandwidth does not change as
CFIL changes, but the jitter peaking, acquisition time, and
loop stability are affected. Figures 6 and 7 show the
open-loop and closed-loop transfer functions.
The PLL zero frequency, fZ, is a function of external
capacitor CFIL, and can be approximated according to:
For an overdamped system (fZ / JBW < 0.25), the jitter
peaking (JP) of a 2nd-order system can be approximat-
ed by:
where JBW is the jitter transfer bandwidth for a given
data rate.
The recommended value of CFIL = 0.82F is to guarantee
a maximum jitter peaking of less than 0.1dB for all data
rates. Decreasing CFIL from the recommended value
decreases acquisition time, with the tradeoff of increased
peaking. For data rates greater than OC-3, CFIL can be
less than 0.82F and still meet the jitter-peaking specifi-
cation.
Excessive reduction of CFIL might cause PLL instability.
CFIL must be a low-TC, high-quality capacitor of type
X7R or better.
J
f
J
P
Z
BW
=+
20
1
log
f
C
Z
FIL
=
Ω
1
2 650
π()
Multirate Clock and Data Recovery
with Limiting Amplifier
10
______________________________________________________________________________________
Table 3. Holdover Frequency Settings
REFERENCE CLOCK FREQUENCY (MHz)
SCLKO FREQUENCY
RS1
RS2
RATESET
FREFSET
666.51
2.667GHz
0
1
0
666.51
666.51MHz
0
1
0
666.51
166.63MHz
1
0
1
0
622.08/625
1.244/1.25GHz
1
0
622.08/625
2.488GHz/2.5GHz
0
622.08
622.08MHz
0
1
0
622.08
155.52MHz
1
0
166.63
2.67GHz
0
1
166.63
666.51MHz
0
1
166.63
166.63MHz
1
0
1
155.52/156.25
1.244/1.25GHz
1
0
1
155.52/156.25
2.488GHz/2.5GHz
0
1
155.52
622.08MHz
0
1
0
1
155.52
155.52MHz
1
0
1
CFIL = 0.82
μF
fZ = 299Hz
CFIL = 0.01
μF
fZ = 24.5kHz
HO(j2
πf) (dB)
OPEN-LOOP
GAIN
1000
f (kHz)
100
10
1
DATA RATE: 2.488Gbps
Figure 6. Open-Loop Transfer Function
CFIL = 0.82
μF
H(j2
πf) (dB)
1000
100
10
1
f (kHz)
-3
0
CLOSED-LOOP
GAIN
CFIL = 0.01
μF
DATA RATE: 2.488Gbps
Figure 7. Closed-Loop Transfer Function
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| MAX3872EVKIT | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Evaluation Kit for the MAX3872 MAX3874 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3873AEGP | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3873AEGP+ | 制造商:Maxim Integrated Products 功能描述:CLOCK RECOVERY 20QFN - Bulk |
| MAX3873AEGP-T | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3873AETP+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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