參數(shù)資料
型號(hào): MAX3872ETJ+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/15頁(yè)
文件大?。?/td> 0K
描述: IC DATA RECOVERY W/AMP 32-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.67GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX3872
Detailed Description
The MAX3872 consists of a fully integrated phase-
locked loop (PLL), limiting amplifier with threshold
adjust, DC-offset cancellation loop, data retiming block,
and CML output buffers (Figure 5). The PLL consists of
a phase/frequency detector, a loop filter, and a voltage-
controlled oscillator (VCO) with programmable dividers.
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
SDI Input Amplifier
The SDI inputs of the MAX3872 accept serial NRZ data
with a differential input amplitude from 10mVP-P up
to1600mVP-P. The input sensitivity is 10mVP-P, at which
the jitter tolerance is met for a BER of 10-10 with thresh-
old adjust disabled. The input sensitivity can be as low
as 4mVP-P and still maintain a BER of 10-10. The
MAX3872 inputs are designed to directly interface with
a transimpedance amplifier such as the MAX3745.
For applications in which vertical threshold adjustment
is needed, the MAX3872 can be connected to the out-
put of an AGC amplifier such as the MAX3861. When
using the threshold adjust, the input voltage range is
50mVP-P to 600mVP-P. See the Design Procedure sec-
tion for decision threshold adjust.
SLBI Input Amplifier
The SLBI input amplifier accepts either NRZ loopback
data or a reference clock signal. This amplifier can
accept a differential input amplitude from 50mVP-P to
800mVP-P.
Phase Detector
The phase detector incorporated in the MAX3872 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
Frequency Detector
The digital frequency detector (FD) acquires frequency
lock without the use of an external reference clock. The
frequency difference between the received data and
the VCO clock is derived by sampling the in-phase and
quadrature VCO outputs on both edges of the data
input signal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequency
detector.
Multirate Clock and Data Recovery
with Limiting Amplifier
8
_______________________________________________________________________________________
CAZ+
RATESET
LOL
LOOP
FILTER
SDO+
SDO-
SLBI+
SLBI-
SIS
FREFSET
LREF
SCLKO+
SCLKO-
CAZ-
FIL
CML
÷ BY
N
CML
AMP
VCTRL
SDI-
SDI+
AMP
D
0
1
Q
PHASE AND
FREQUENCY
DETECTOR
BANDGAP
REFERENCE
VCO
VREF
LOGIC
DC-OFFSET
CANCELLATION
LOOP
THRESHOLD
ADJUST
MAX3872
RS1
RS2
Figure 5. Functional Diagram
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MAX3873AEGP-T 功能描述:計(jì)時(shí)器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
MAX3873AETP+ 功能描述:計(jì)時(shí)器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel