參數(shù)資料
型號: MAX3872EGJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: Multirate Clock and Data Recovery with Limiting Amplifier
中文描述: CLOCK RECOVERY CIRCUIT, QCC32
封裝: 5 X 5 MM, 0.90 MM HEIGHT, MO-220, QFN-32
文件頁數(shù): 12/13頁
文件大小: 580K
代理商: MAX3872EGJ
M
Consecutive Identical Digits (CIDs)
The MAX3872 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER better than 10
-10
. The CID tolerance
is tested using a 2
13
- 1 PRBS with long runs of ones
and zeros inserted in the pattern. A CID tolerance of
2000 bits is typical.
Exposed Pad (EP) Package
The EP 32-pin QFN incorporates features that provide a
very-low thermal-resistance path for heat removal from
the IC. The pad is electrical ground on the MAX3872
and should be soldered to the circuit board for proper
thermal and electrical performance.
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3872 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
V
CC
as possible. To reduce feedthrough, isolate the
input signals from the output signals. If a bare die is
used, mount the back of die to ground (GND) potential.
Multirate Clock and Data Recovery
with Limiting Amplifier
12
______________________________________________________________________________________
3
3
3
2
2
2
2
9
1
1
1
1
1
1
18
19
20
21
22
23
24
7
6
5
4
3
2
1
MAX3872
5mm x 5mm
32 QFN
TOP VIEW
SDI+
V
CC
SDI-
V
CC
SLBI+
SLBI-
SIS
8
LREF
G
V
C
V
R
C
C
V
C
F
2
G
VCC_OUT
SDO+
SDO-
VCC_OUT
SCLKO+
SCLKO-
VCC_VCO
17
RATESET
R
R
1
G
V
F
G
G
L
Pin Configuration
SDI+
CAZ-
R1
TTL
R1 + R2
50k
R2
CAZ+
FREFSET
0.1
μ
F
SDI-
SLBI-
V
REF
SIS
LREF
LOL
155.52MHz
REFERENCE CLOCK
V
CTRL
MAX3872
SLBI+
CML
CML
SDO+
SDO-
SCLKO-
0.82
μ
F
SCLKO+
TIA OUTPUT
(2.488Gbps)
RATESET
RS2
RS1
GND
+3.3V
VCC
+3.3V
VCC_VCO
FIL
+3.3V
+3.3V
MAX3861
AGC AMPLIFIER
Figure 10. Interfacing with the MAX3861 AGC Using Threshold
Adjust
Chip Information
TRANSISTOR COUNT: 5142
PROCESS: SiGe BiPOLAR
SUBSTRATE: SOI
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