
M
Upstream CAT V Driver Amplifier
8
_______________________________________________________________________________________
Some allowance must be made for parasitic inductance
in the transformer as well as on the printed circuit
board. Therefore, choose a resistance value lower than
a perfect match. Two 8.0
resistors will provide a near-
optimum match.
If the output match is less than critical, the back-termina-
tion resistors can be set to a lower value. This will extend
the upper limit of the output level range (by dropping less
voltage across the resistors and more across the load),
and may improve distortion performance for a given out-
put level.
Layout Issues
A well designed printed circuit board is an essential
part of an RF circuit. For best performance pay atten-
tion to power-supply layout issues, as well the output
circuit layout.
Output Circuit Layout
The differential implementation of the MAX3532’s out-
put has the benefit of significantly reducing even-order
distortion, the most significant of which is second-har-
monic distortion. The degree of distortion cancellation
depends on the amplitude and phase balance of the
overall circuit. It is critical that the traces leading from
the output pins be exactly the same length.
Since the MAX3532 has a low-impedance output, the
output traces must also be kept as short as possible,
as small amounts of inductance can have an impact at
higher frequencies. The back-termination resistors
should be kept as close to the device as possible.
Power-Supply Layout
For minimal coupling between different sections of the
IC, the ideal power-supply layout is a star configuration.
This configuration has a large valued decoupling
capacitor at the central V
CC
node. The V
CC
traces
branch out from this node, each going to a separate
V
CC
node in the MAX3532 circuit. At the end of each of
these traces is a decoupling capacitor that provides a
very low impedance at the frequency of interest. This
arrangement provides local V
CC
decoupling at each
V
CC
pin.
The traces leading from the supply to V
CC
(pin 29) and
V
CC
2 (pin 30) must be made as thick as practical to
keep resistance well below 1
.
Ground inductance degrades distortion performance.
Therefore, ground plane connections to V
EE
(pin 26)
and V
EE2
(pin 31) should be made with multiple vias if
possible.
Chip Information
TRANSISTOR COUNT: 1100
________________________________________________________Pac kage Information
S