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參數(shù)資料
| 型號： | MAX3532 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Upstream CATV Driver Amplifier |
| 中文描述： | CATV上行驅(qū)動放大器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 84K |
| 代理商： | MAX3532 |
M
_______________Detailed Desc ription
The following sections describe the blocks shown in the
Functional Diagram (Figure 1).
Programmable-Gain Amplifier
The MAX3532’s processing path is made up of the pro-
grammable-gain amplifier (PGA) and the transmit
power amplifier, which together provide better than
64dB of output level control in 1dB steps.
The PGA is implemented as a programmable Gilbert
cell attenuator. It uses a differential architecture to
achieve maximum linearity. When it is driven single
ended, specified performance is achieved given that
the unused input is decoupled to ground. The gain of
the PGA is determined by the serial-data interface. See
Table 2.
T ransmit Power Amplifier
The transmit power amp is capable of driving +8dBmV
to +62dBmV differentially when driven with +36dBmV. To
achieve the necessary swing from a single +5V supply,
an external 1:2 transformer must be used. The output of
the transmit power amplifier is a very low-impedance
emitter follower, which requires two 8
series termination
resistors to achieve adequate output return loss.
The power amplifier’s gain is set via the serial-data
interface. The transmit power amplifier has a switchable
+16dB or +0dB gain to achieve high linearity or low
noise, respectively. High-gain mode sets the power
amp’s gain to +16dB, allowing for the highest output
signal swings. Low-noise mode sets the gain to 0dB,
which achieves the lowest output noise.
S hutdown Mode
In normal operation the shutdown pin (
SHDN
) is driven
high. When
SHDN
is asserted low, all circuits within the
IC are disabled. Only leakage currents flow in this
state. Data stored within the serial-data interface latch-
es will be lost upon shutting down the part.
T ransmit-Disable Mode
When the TXEN pin is asserted high, the device is in
transmit mode. When TXEN is driven low, the transmit
amplifier switches to common-mode operation and the
output signal appears at the output pins VOUT+ and
VOUT- with the same phase. These identical signals
cancel within the output transformer core, providing
high isolation from input to output. Optimum isolation is
achieved in low-noise mode with a low gain setting.
S erial Interfac e
The serial interface has an active-low enable (
CS
) to
bracket the data, with data clocked in MSB first on the
rising edge of SCLK. Data is stored in the storage latch
on the rising edge of
CS
. The serial interface controls
the state of the PGA and output amplifier. The register
format is shown in Tables 1 and 2. Serial-interface tim-
ing is shown in Figure 2.
Transmit Modes
The hardware TXEN line is ANDed with software bit D7,
so both TXEN and D7 must be high to transmit. Bit D6
governs whether the device is set to high-gain mode (D6
= 1) or to low-noise mode (D6 = 0). High-power mode
should be used for output levels above 45dBmV. This
transition point optimizes the MAX3532’s distortion perfor-
mance, but either mode may be used throughout the full
complement of programmed gain states. Bits D5–D0
define 64 PGA gain states, nominally 1dB each.
Upstream CAT V Driver Amplifier
6
_______________________________________________________________________________________
MAX3532
VOUT-
VIN+
PGA
SHDN
VIN-
CS
SDA
SCLK
VOUT+
TXEN
SERIAL-DATA INTERFACE
BIAS
Figure 1. Functional Diagram
BIT
MNEMONIC
DESCRIPTION
MSB 7
D7
Chip-State Control MSB
6
D6
Chip-State Control LSB
5
D5
Gain Control, Bit 5
4
D4
Gain Control, Bit 4
3
D3
Gain Control, Bit 3
2
D2
Gain Control, Bit 2
1
D1
Gain Control, Bit 1
LSB 0
D0
Gain Control, Bit 0
Table 1. Serial-Interface Control Words
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