參數(shù)資料
型號: MAX3421EETJ+
廠商: Maxim Integrated Products
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: IC USB PERIPH/HOST CNTRL 32TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
控制器類型: USB 外設(shè)控制器
接口: USB/串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 15mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 1407 (CN2011-ZH PDF)
配用: MAX3421EVKIT-1+-ND - EVAL KIT FOR MAX3421E
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
5
Maxim Integrated
Pin Description
PIN
NAME
INPUT/
OUTPUT
FUNCTION
1
GPIN7
Input
General-Purpose Input. GPIN7–GPIN0 are connected to VL with internal pullup resistors.
GPIN7–GPIN0 logic levels are referenced to the voltage on VL.
2VL
Input
Level-Translator Voltage Input. Connect VL to the system’s 1.4V to 3.6V logic-level power
supply. Bypass VL to ground with a 0.1F capacitor as close to VL as possible.
3, 19
GND
Input
Ground
4
GPOUT0
5
GPOUT1
6
GPOUT2
7
GPOUT3
8
GPOUT4
9
GPOUT5
10
GPOUT6
11
GPOUT7
Output
General-Purpose Push-Pull Outputs. GPOUT7–GPOUT0 logic levels are referenced to the
voltage on VL.
12
RES
Input
Device Reset. Drive
RES low to clear all of the internal registers except for PINCTL (R17),
USBCTL (R15), and SPI logic. The logic level is referenced to the voltage on VL. (See the
Device Reset section for a description of resets available on the MAX3421E.) Note: The
MAX3421E is internally reset if either VCC or VL is not present. The register file is not accessible
under these conditions.
13
SCLK
Input
SPI Serial-Clock Input. An external SPI master supplies SCLK with frequencies up to 26MHz. The
logic level is referenced to the voltage on VL. Data is clocked into the SPI slave interface on the
rising edge of SCLK. Data is clocked out of the SPI slave interface on the falling edge of SCLK.
14
SS
Input
SPI Slave Select Input. The
SS logic level is referenced to the voltage on VL. When SS is driven
high, the SPI slave interface is not selected, the MISO pin is high impedance, and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low
SS transition and ends with a
low-to-high
SS transition.
15
MISO
Output
SPI Serial-Data Output (Master-In Slave-Out). MISO is a push-pull output. MISO is tri-stated in
half-duplex mode or when
SS = 1. The MISO logic level is referenced to the voltage on VL.
16
MOSI
Input or
Input/
Output
SPI Serial-Data Input (Master-Out Slave-In). The logic level on MOSI is referenced to the
voltage on VL. MOSI can also be configured as a bidirectional MOSI/MISO input and output.
(See Figure 15.)
17
GPX
Output
General-Purpose Multiplexed Push-Pull Output. The internal MAX3421E signal that appears on
GPX is programmable by writing to the GPXB and GPXA bits of the PINCTL (R17) register and the
SEPIRQ bit of the MODE (R27) register. GPX indicates one of five signals (see the GPX section).
18
INT
Output
Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage on VL and is
a push-pull output with programmable polarity. In level mode, INT is open-drain and active low.
Set the IE bit in the CPUCTL (R16) register to enable INT.
20
D-
Input/
Output
USB D- Signal. Connect D- to a USB connector through a 33
Ω ±1% series resistor. A
switchable 15k
Ω D- pulldown resistor is internal to the device.
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