參數(shù)資料
型號: MAX3349EAEBE+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/17頁
文件大小: 0K
描述: IC TXRX USB 2.0 FS 16-UCSP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: USB 2.0
電源電壓: 4 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-WFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 16-UCSP(2x2)
包裝: 帶卷 (TR)
MAX3349EA
USB 2.0 Full-Speed Transceiver with UART
Multiplexing Mode
10
______________________________________________________________________________________
GND with a 0.1F ceramic capacitor as close to the
device as possible. There are high-impedance resistors
~2M
to ground on D+ and D- to prevent floating
nodes when in UART mode and nothing is connected.
Operating Modes
The MAX3349EA operates in either USB mode or
UART mode, depending on the presence or absence
of VBUS. Bus detect output BD is logic-high when a
voltage higher than VTH-VBUS is applied to VBUS, and
logic-low otherwise. The MAX3349EA operates in USB
mode when BD is logic-high, and UART mode when
BD is logic-low.
USB Mode
In USB mode, the MAX3349EA implements a full-speed
(12Mbps) USB interface on D+ and D-, with enumerate
and suspend functions. A differential USB receiver pre-
sents the USB state as a logic-level output RCV (Table
3a). VP/VM are outputs of single-ended USB receivers
when OE is logic-high, allowing detection of single-
ended 0 (SE0) events. When OE is logic-low, VP and
VM serve as inputs to the USB transmitter. Drive sus-
pend input SUS logic-high to force the MAX3349EA into
a low-power operating mode and disable the differen-
tial USB receiver (Table 3b).
UART Mode
The MAX3349EA operates in UART mode when BD is
logic-low (VBUS not present). The Rx signal is the out-
put of a single-ended receiver on D+, and the Tx input
is driven out on D-. Signaling voltage thresholds for D+
and D- are determined by VUART, an externally applied
voltage between +2.7V and +3.3V.
Power-Supply Configurations
VL Logic Supply
In both USB and UART modes, the control interface is
powered from VL. The MAX3349EA operates with logic-
side voltage (VL) as low as +1.4V, providing level shift-
ing for lower voltage ASICs and microcontrollers.
Timing Diagrams (continued)
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 10. Human Body Model Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50M
to 100M
RD
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 11. IEC61000-4-2 ESD Contact Discharge Test Model
tR = 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
I PEAK
I
Figure 12. IEC 61000-4-2 Contact Discharge Model Current
Waveform
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