參數(shù)資料
型號: MAX3140CEI+
廠商: Maxim Integrated Products
文件頁數(shù): 19/36頁
文件大小: 0K
描述: IC UART SPI MICRWR W/TXRX 28QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
特點: 收發(fā)器
FIFO's: 8 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 4.75 V ~ 5.25 V
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-QSOP
供應(yīng)商設(shè)備封裝: 28-QSOP
包裝: 管件
產(chǎn)品目錄頁面: 1404 (CN2011-ZH PDF)
MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
26
______________________________________________________________________________________
START
STOP
START
STOP
NORMAL
RX
UART FRAME
DATA BITS
01
1
00
0
NORMAL UART
TX
11
1
00
0
IrDA
RX
IrDA
TX
Figure 16. IrDA Timing
100kHz/div
0
1MHz
20dB/div
MAX3140
FIG17
Figure 17. Driver Output Waveform and FFT Plot of MAX3140
with SRL = GND, Transmitting at 20kHz
9-Bit Networks
The MAX3140 supports a common multidrop communi-
cation technique referred to as 9-bit mode. In this
mode, the parity bit is set to indicate a message that
contains a header with a destination address. Set the
MAX3140’s parity mask to generate interrupts for this
condition. Operating a network in this mode reduces
the processing overhead of all nodes by enabling the
slave controllers to ignore most message traffic. This
relieves the remote processor to handle more useful
tasks.
In 9-bit mode, the MAX3140 is set up with eight bits
plus parity. The parity bit in all normal messages is
clear, but is set in an address-type message. The
MAX3140’s parity-interrupt mask generates an interrupt
on high parity when enabled. When the master sends
an address message with the parity bit set, all
MAX3140 nodes issue an interrupt. All nodes then
retrieve the received byte to compare to their assigned
address. Once addressed, the node continues to
process each received byte. If the node was not
addressed, it ignores all message traffic until a new
address is sent out by the master.
The parity/9th-bit interrupt is controlled only by the data
in the receive register and is not affected by data in the
FIFO, so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled,
received nonaddress words are ignored and not even
read from the UART.
SIR IrDA Mode
The MAX3140’s IrDA mode communicates with other
IrDA SIR-compatible devices, or reduces power con-
sumption in opto-isolated applications.
In IrDA mode, a bit period is shortened to 3/16 of a
baud period (1.61s at 115,200 baud) (Figure 16). A
data zero is transmitted as a pulse of light (TX = logic
low, RX = logic high).
In receive mode, the RX signal’s sampling is done
halfway into the transmission of a high level. The sam-
pling is done once, instead of three times, as in normal
mode. The MAX3140 ignores pulses shorter than
approximately 1/16 of the baud period. The IrDA device
that is communicating with the MAX3140 must transmit
pulses at 3/16 of the baud period. For compatibility with
other IrDA devices, set the format to 8-bit data, one
stop, no parity.
256 RS-485 Transceivers on the Bus
The standard RS-485 receiver input impedance is 12k
Ω
(one unit load), and the standard driver can drive up to
32 unit loads. The MAX3140 has a 1/8-unit-load receiver
input impedance (96k
Ω), allowing up to 256 trans-
ceivers to be connected in parallel on one communica-
tion line. Any combination of these devices and/or other
RS-485 transceivers with a total of 32 unit loads or less
can be connected to the line.
Reduced EMI and Reflections for the
RS-485/RS-422 Driver
The MAX3140 with SRL = VCC or unconnected, is slew-
rate limited, minimizing EMI and reducing reflections
caused by improperly terminated cables. Figure 17
shows the driver output waveform and its Fourier analy-
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