參數(shù)資料
型號(hào)： MAX3110ECNI+G36
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 20/31頁(yè)
文件大小： 0K
描述： IC TXRX RS232 SPI W/CAP 28-DIP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 14
特點(diǎn)： 收發(fā)器
通道數(shù)： 1，UART
規(guī)程： RS232，RS485
電源電壓： 4.5 V ~ 5.5 V
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶CMOS： 是
安裝類(lèi)型： 通孔
封裝/外殼： 28-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1404 (CN2011-ZH PDF)
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
In 9-bit mode, the MAX3110E/MAX3111E is set up with
eight bits plus parity. The parity bit in all normal mes-
sages is clear but is set in an address-type message.
The MAX3110E/MAX3111E’s parity-interrupt mask gen-
erates an interrupt on high parity when enabled. When
the master sends an address message with the parity
bit set, all MAX3110E/MAX3111E nodes issue an inter-
rupt. All nodes then retrieve the received byte to com-
pare to their assigned address. Once addressed, the
node continues to process each received byte. If the
node was not addressed, it ignores all message traffic
until a new address is sent out by the master.
The parity/9th-bit interrupt is controlled only by the data
in the receive register and is not affected by data in the
FIFO, so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled,
received non-address words can be ignored and not
even read from the UART. For more detailed informa-
tion on 9-bit mode, refer to the MAX3100 data sheet.
SIR IrDA Mode
The MAX3110E/MAX3111E’s IrDA mode can be used
to communicate with other IrDA SIR-compatible
devices or to reduce power consumption in opto-isolat-
ed applications.
In IrDA mode, a bit period is shortened to 3/16 of a
baud period (1.61s at 115,200 baud). A data zero is
transmitted as a pulse of light (TX pin = logic low, RX
pin = logic high), as shown in Figure 15.
In receive mode, the RX signal’s sampling is done
halfway into the transmission of a high level. The sam-
pling is done once (instead of three times, as in normal
mode). The MAX3110E/MAX3111E ignore pulses short-
er than approximately 1/16 of the baud period. The
IrDA device that is communicating with the MAX3110E/
MAX3111E must be set to transmit pulses at 3/16 of the
baud period. For compatibility with other IrDA devices,
set the format to 8-bit data, one stop, no parity. For
more detailed information on SIR IrDA mode, refer to
the MAX3100 data sheet.
Layout and Power-Supply
_____________________Considerations
The MAX3110E/MAX3111E require basic layout tech-
niques and fundamental power supply considerations.
The minimum requirements include: (1) placing a 1F
ceramic bypass capacitor as close as possible to VCC,
preferably right next to the VCC lead or on the opposite
side of the PCB directly below the VCC lead; (2) using
an internal ground plane within the PCB, returning all
circuit grounds to this ground plane, or using a ‘star’
ground technique where all circuit grounds are
returned to a common ground point at the ‘GND’ lead
of the IC; (3) ensuring that the power source to the IC
has a low inductive path and is high-frequency
bypassed to absorb ESD events with significant
changes in the supply voltage.
START
STOP
START
STOP
NORMAL
RX
UART FRAME
DATA BITS
01
1
00
0
NORMAL UART
TX
11
1
00
0
IrDA
RX
IrDA
TX
Figure 15. IrDA Timing
Maxim Integrated
27
MAX3110E/MAX3111E
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