參數(shù)資料
型號: MAX3110ECNI+G36
廠商: Maxim Integrated Products
文件頁數(shù): 9/31頁
文件大?。?/td> 0K
描述: IC TXRX RS232 SPI W/CAP 28-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 14
特點(diǎn): 收發(fā)器
通道數(shù): 1,UART
規(guī)程: RS232,RS485
電源電壓: 4.5 V ~ 5.5 V
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 28-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
產(chǎn)品目錄頁面: 1404 (CN2011-ZH PDF)
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 3. Read Configuration (D15, D14 = 0, 1)
Notes:
bit 15: DOUT
R = 1, Data is available to be read or is being read from the
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bit 13: DOUT
FEN = 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DOUT
SHDNo = 1, Software shutdown is enabled.
SHDNo = 0, Software shutdown is disabled.
bit 11: DOUT
TM = 1, Transmit buffer empty interrupt is enabled.
TM = 0, Transmit buffer empty interrupt is disabled.
bit 10: DOUT
RM = 1, Data available in the receive register or FIFO interrupt
is enabled.
RM = 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DOUT
PM = 1, Parity bit high received interrupt is enabled.
PM = 0, Parity bit received interrupt is disabled.
bit 8: DOUT
RAM = 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM = 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DOUT
IR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DOUT
ST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DOUT
PE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DOUT
L = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DOUT
B3–B0 = XXXX Baud-Rate Divisor Select Bits (see Table 6)
bit 15, 14: DIN
0,1 = Read Configuration
bits 13–1: DIN
Zeros
bit 0: DIN
If TEST = 1 and CS = 0, then RTS =16xBaudCLK
TEST = 0, Disables test mode
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
14
1
T
6
0
ST
7
0
IR
15
2
DIN
0
DOUT
R
B2
BIT
3
0
B3
0
TEST
B0
1
0
B1
4
0
L
5
0
PE
10
0
RM
11
0
TM
8
0
RAM
9
0
PM
12
0
SHDNo
13
0
FEN
Maxim Integrated
17
MAX3110E/MAX3111E
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