SPI/I2C UART with 128-Word FIFOs in WLP MAX3108 17 Maxim Integrated The followin" />
參數(shù)資料
型號: MAX3108EWA+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/56頁
文件大?。?/td> 0K
描述: IC UART
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
17
Maxim Integrated
The following three error conditions are checked for each
received word: parity error, frame error, and noise on the
line. Parity errors are detected by calculating either even
or odd parity of the received word as programmed by
register settings. Framing errors are detected when the
received data frame does not match the expected frame
format in length. Line noise is detected by checking the
logical congruency of the three samples taken of each
bit (Figure 6).
The receiver can be turned off by setting the MODE1[0]:
RxDisabl bit high. After this bit is set high, the MAX3108
turns the receiver off immediately following the current
word and does not receive any further data.
The RX input logic can be inverted by setting the IrDA[4]:
RxInv bit high. Unless otherwise noted, all receiver logic
described in this data sheet assumes that RxInv is set
low.
Line Noise Indication
When operating in standard or 2x (i.e., not 4x) rate mode,
the MAX3108 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples per received bit have differing logic
levels, then noise on the transmission line has affected
the received data and it is considered to be noisy. This
noise indication is reflected in the LSR[5]: RxNoise bit for
each received byte. Parity errors are another indication
of noise, but are not as sensitive.
Figure 6. Midbit Sampling
Figure 7. Clock Selection Diagram
1
RX
BAUD
BLOCK
23
45
67
89
ONE BIT PERIOD
10
11
MAJORITY
CENTER
SAMPLER
12
13
14
15
16
A
CRYSTAL
OSCILLATOR
XOUT
CrystalEn
XIN
BAUD-RATE
GENERATOR
PLLBypass
PLLEn
PLL
PREDIVIDER
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