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參數(shù)資料
| 型號： | MAX3108EWA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓模塊： | Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
36
Maxim Integrated
MODE2 Register
Bit 7: EchoSuprs
Set the EchoSuprs bit high to discard any data that the MAX3108 receives when its transmitter is busy transmit-
ting. In half-duplex communication such as RS-485 and IrDA, this allows blocking of the locally echoed data. The
receiver can block data for an extended time after the transmitter ceases transmission by programming a hold time in
HDplxDelay[3:0].
Bit 6: MultiDrop
Set the MultiDrop bit high to enable the 9-bit multidrop mode. If this bit is set, parity checking is not performed by the
receiver and parity generation is not done by the transmitter. The address/data indication takes the place of the parity
bit in received and transmitted data words. The parity error interrupt in LSR[2] has a different meaning in multidrop
mode: it represents the 9th bit (address/data indication) that is received with each 9-bit data character.
Bit 5: Loopback
Set the Loopback bit high to enable internal local loopback mode. This internally connects TX to RX and also RTS
to CTS. In local loopback mode, the TX output and the RX input are disconnected from the internal transmitter and
receiver. The TX output is in three-state. The RTS output remains connected to the internal logic and reflects the logic
state programmed in LCR[7]. The CTS input is disconnected from RTS and the internal logic. CTS thus remains in a
high-impedance state.
Bit 4: SpecialChr
Set the SpecialChr bit high to enable special character detection. The receiver can detect up to four special characters,
as selected in FlowCtrl[5:4] and defined in the XON1, XON2, XOFF1, and/or XOFF2 registers, optionally in combina-
tion with GPIOx inputs if enabled through FlowCtrl[2]: GPIAddr. When a special character is received, it is put into the
RxFIFO and a special character detect interrupt is generated in ISR[1].
Special character detection can be used in addition to auto XON/XOFF flow control if enabled by FlowCtrl[3]:
SwFlowEn. In this case, XON/XOFF flow control is limited to single byte XON and XOFF characters (XON1 and XOFF1),
and only two special characters can be defined (XON2 and XOFF2).
Bit 3: RFifoEmtyInv
Set the RFifoEmtyInv bit high to invert the meaning of the receiver empty interrupt in ISR[6]: RFifoEmptyInt. If
RFifoEmtyInv is set low, RFifoEmptyInt is generated when the receive FIFO is empty. If RFifoEmtyInv is set high,
RFifoEmptyInt is generated when data is put into the empty receive FIFO.
Bit 2: RxTrgInv
Set the RxTrgInv bit high to invert the meaning of the RxFIFO triggering. If the RxTrgInv bit is set low, an interrupt
is generated in ISR[3]: RxTrigInt when the RxFIFO fill level is filled up to above the trigger level programmed into
FIFOTrgLvl[7:4]. If RxTrgInv is set high, an interrupt is generated in ISR[3] when the RxFIFO is emptied to below the
trigger level programmed into FIFOTrgLvl[7:4].
Bit 1: FIFORst
Set the FIFORst bit high to clear all data contents from both the receive and transmit FIFOs. After a FIFO reset, set
FIFORst low to continue normal operation.
Bit 0: RST
Set the RST bit high to initiate software reset for the MAX3108. The I2C/SPI bus stays active during this reset; com-
munication with the MAX3108 is possible while RST is set. All register bits are reset to their reset state and all FIFOs
are cleared during a reset.
Set RST low to continue normal operation after a software reset. The MAX3108 requires reprogramming following a
software reset.
ADDRESS:
0x0A
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
EchoSuprs
MultiDrop
Loopback
SpecialChr
RFifoEmptyInv
RxTrgInv
FIFORst
RST
RESET
0
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