參數(shù)資料
型號(hào)： MAX3000A
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 31/42頁(yè)
文件大?。?/td> 649K
代理商： MAX3000A
Altera Corporation
31
MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3256A Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
t
IN
t
IO
t
SEXP
t
PEXP
t
LAD
t
LAC
t
IOE
t
OD1
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V
CCIO
= 3.3 V
Output buffer and pad delay,
slow slew rate = off
V
CCIO
= 2.5 V
Output buffer and pad delay,
slow slew rate = on
V
CCIO
= 2.5 V or 3.3 V
Output buffer enable delay, slow
slew rate = off V
CCIO
= 3.3 V
Output buffer enable delay, slow
slew rate = off V
CCIO
= 2.5 V
Output buffer enable delay, slow
slew rate = on
V
CCIO
= 2.5 V or 3.3 V
Output buffer disable delay
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low–power adder
0.9
0.9
2.8
0.5
2.2
1.0
0.0
1.2
1.2
1.2
3.7
0.6
2.8
1.3
0.0
1.6
ns
ns
ns
ns
ns
ns
ns
ns
C1 = 35 pF
t
OD2
C1 = 35 pF
1.7
2.1
ns
t
OD3
C1 = 35 pF
6.2
6.6
ns
t
ZX1
C1 = 35 pF
4.0
5.0
ns
t
ZX2
C1 = 35 pF
4.5
5.5
ns
t
ZX3
C1 = 35 pF
9.0
10.0
ns
t
XZ
t
SU
t
H
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
C1 = 5 pF
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.1
0.9
2.9
1.2
1.2
0.8
1.6
1.0
1.5
2.3
2.3
2.4
4.0
1.6
1.2
2.1
1.3
2.0
3.0
3.0
3.2
5.0
(2)
(5)
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MAX-3000A 制造商:ALTERA 制造商全稱(chēng):Altera Corporation 功能描述:Programmable Logic Device Family
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