參數(shù)資料
型號: MAX3000A
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 26/42頁
文件大?。?/td> 649K
代理商: MAX3000A
26
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
t
CLR
t
PIA
t
LPA
Register clear time
PIA delay
Low–power adder
1.2
0.9
2.5
1.9
1.5
4.0
2.6
2.1
5.0
ns
ns
ns
(2)
(5)
Table 15. EPM3064A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–4
–7
–10
Min
Max
Min
Max
Min
Max
t
PD1
Input to non–registered
output
I/O input to non–registered
output
Global clock setup time
Global clock hold time
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock period
(2)
Maximum internal array
clock frequency
C1 = 35 pF
(2)
4.5
7.5
10.0
ns
t
PD2
C1 = 35 pF
(2)
4.5
7.5
10.0
ns
t
SU
t
H
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
(2)
(2)
2.8
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
4.7
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
6.2
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.1
5.1
7.0
(2)
(2)
C1 = 35 pF
(2)
4.3
7.2
9.6
(3)
t
CNT
(2)
4.5
7.4
10.0
ns
f
CNT
(2)
,
(4)
222.2
135.1
100.0
MHz
t
ACNT
f
ACNT
4.5
7.4
10.0
ns
MHz
(2)
,
(4)
222.2
135.1
100.0
Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–4
–7
–10
Min
Max
Min
Max
Min
Max
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