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參數(shù)資料
| 型號： | MAX2986 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Integrated Powerline Digital Transceiver |
| 中文描述： | 集成電力線數(shù)字收發(fā)器 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 349K |
| 代理商： | MAX2986 |
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M
Integrated Powerline Digital Transceiver
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9
RXCLK
CLOCK SOURCE (2.5MHz OR 25MHz)
TXCLK
TXEN
RXDV
CRS
TXD[3:0]
RXD[3:0]
RXER
MDC
MDIO
COL
GND
MIITXEN
MIICLK
MIIRXDV
MIICRS
MIIDAT[3:0]
MIIDAT[7:4]
MIIRXER
MIIMDC
MIIMDIO
BUFWR
BUFRD
BUFCS
V
CC
ETHERNET
802.3 MAC
(MII)
MII
INTERFACE
MAC
MAX2986
PHY
Figure 3. MAC and PHY Connection in MII Mode
MII MAC and PHY Connections
Figure 3 illustrates the connections between MAC and
PHY in MII mode. Although the Tx and Rx data paths
are full duplex, the MII interface is operated in half-
duplex mode. MIIRXDV is never asserted at the same
time as MIITXEN.
On transmit, the MAX2986 asserts MIICRS some time
after MIITXEN is asserted, and drops MIICRS after
MIITXEN is deasserted and when the MAX2986 is
ready to receive another packet. When MIICRS falls,
the Ethernet MAC times out an interframe gap (IFG)
(0.96μs typ) and asserts MIITXEN again if there is
another packet to send. This differs from the nominal
behavior of MIICRS in that MIICRS can extend past the
end of the packet by an arbitrary amount of time, while
the MAX2986 is gaining access to the channel and
transmitting the packet.
MACs in 10Mbps mode do not use a jabber timeout, so
there is no timing restriction on how long MIICRS can
assert (other than timeouts the MAX2986 may implement).
Transmissions are modulated onto the wire as soon as
the transfer begins, as the MII fills the MAX2986 buffer
faster than data needs to be made available to the
modulator. When a packet arrives at the MAX2986, it
attempts to gain access to the channel. This may not
happen before the entire packet is transferred across
the MII interface, so the MAX2986 buffers at least one
Ethernet packet to perform this rate adaptation.
On receive, when the MAX2986 anticipates that it will
have a packet demodulated, it raises MIICRS to seize
the half-duplex MII channel, waits a short time (an IFG),
then possibly defers to MIITXEN (which may just have
been asserted) plus an IFG, and then raises MIIRXDV
to transfer the packet. At the end of the transfer, it
drops MIICRS unless the transmit buffer is full or there
is another receive packet ready to transfer. This is illus-
trated in Figure 4, where one receive transfer is fol-
lowed by a second, which defers to MIITXEN. Data
reception needs to have priority over transmission to
ensure that the buffer empties faster than packets
arrive off the wire. The longest the receiver needs to
wait is the time to transfer one Tx frame plus an IFG or
approximately 134μs. However, minimum size frames
can arrive at a peak rate of one every 65μs, so the
receive-side buffer must accommodate multiple frames
(but only a little more than one Ethernet packet of data).
MIICRS
MIIRXDV
MIITXEN
RECEIVE
INCOMING
IFG
DEFER
Figure 4. Receive Defer in MII Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX2986CXE | 制造商:Maxim Integrated Products 功能描述:PLDC (HOMEPLUG 1.0) BASEBAND W/O MAC - Rail/Tube |
| MAX2986CXE+ | 制造商:Maxim Integrated Products 功能描述:PLDC (HOMEPLUG 1.0) BASEBAND W/O MAC - Rail/Tube |
| MAX2986CXE+D | 功能描述:電信線路管理 IC Integrated Powerline Digital Transceiver RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| MAX2986CXE+T | 制造商:Maxim Integrated Products 功能描述:PLDC (HOMEPLUG 1.0) BASEBAND W/O MAC - Tape and Reel |
| MAX2986CXE-D | 功能描述:電信線路管理 IC PLDC (HOMEPLUG 1.0) BASEBAND W/O MAC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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