參數(shù)資料
型號(hào): MAX2078CTK+
廠商: Maxim Integrated Products
文件頁數(shù): 25/26頁
文件大小: 0K
描述: IC FRNT-END ULTRASOUND 8CH 68QFN
應(yīng)用說明: Ultrasound Imaging Systems Application Note
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
特色產(chǎn)品: MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers
標(biāo)準(zhǔn)包裝: 30
類型: 超聲波接收器
應(yīng)用: 醫(yī)療用超聲波成像,聲納
安裝類型: 表面貼裝
封裝/外殼: 68-TQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-TQFN-EP(10x10)
包裝: 管件
MAX2078
Octal-Channel Ultrasound Front-End
with CW Doppler Mixers
8
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS—SERIAL PERIPHERAL INTERFACE
(DOUT loaded with 60pF and 10M
Ω, 2ns rise and fall edges on CLK.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Speed
10
MHz
Mininimum Data-to-Clock Setup
Time
tCS
5ns
Mininimum Data-to-Clock Hold
Time
tCH
0ns
Mininimum Clock-to-
CS Setup
Time
tES
5ns
CS Positive Mininimum Pulse
Width
tEW
1ns
Mininimum Clock Pulse Width
tCW
2ns
Mininimum
CS High to Mixer
Clock on
tMIXCS
2ns
Note 5:
Minimum and maximum limits at TA = +25°C and +70°C are guaranteed by design, characterization, and/or production test.
Note 6:
Noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF.
Note 7:
Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes a period of time (related to the RC time constant) when the DC level on the chip side of
the capacitor is outside the acceptable common-mode range and the LO swing does not excede both of the logic thresh-
olds required for proper operation. This problem associated with AC-coupling causes an inability to ensure synchronization
among beamforming channels. The LVDS signal is terminated differentially with an external 100
Ω resistor on the board.
Note 8:
An external 100
Ω resistor terminates the LVDS differential signal path.
Note 9:
Total on-chip power dissipation is calculated as PDISS = VCC1 x ICC1 + VCC2 x ICC2 + VREF x IREF + [11V - (I11V/4) x 162] x
I11V.
Note 10: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time may be excessive
and a switching network is recommended, as shown in the
Applications Information section.
Note 11: See the
Ultrasound-Specific IMD3 Specification section.
Note 12: The reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8
channels. If more channels are used, the reference noise must be reduced to get the best noise performance.
Note 13: Channel-to-channel gain and phase matching measured on 30 pieces during engineering characterization at room tem-
perature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the
angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the
phase variation.
Note 14: Voltage gain is measured by subtracting the output-voltage signal from the input-voltage signal. The output-voltage signal
is obtained by taking the differential CW I output and summing it in quadrature with the differential CW Q output. The input
voltage is defined as the differential voltage applied to the CW input pins.
Note 15: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 16: Transconductance is defined as the quadrature-combined CW differential output current at baseband divided by the
mixer’s input voltage.
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