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參數(shù)資料
| 型號： | MAX2038CCQ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VGA W/OCTAL MIXER 8CH 100TQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 類型： | 可變增益放大器 |
| 應用： | 醫(yī)療用超聲波成像，聲納 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
20
______________________________________________________________________________________
Serial Interface
The serial interface of the MAX2038 programs the LO for
16, 8, or 4 quadrature phases using a serial shift register
implementation. Data is shifted into the device on DIN.
The serial shift register clock is applied to the CLK input.
The serial shift register has 5 bits per channel. The first 4
bits are for phase programming, and the fifth bit enables
or disables each channel of the mixer array.
Each mixer can be programmed to 1 of 16 phases;
therefore, 4 bits are required for each channel for pro-
gramming. The master high-frequency mixer clock is
applied to differential inputs LO_LVDS+ and LO_LVDS-
(for modes 1 and 2) and LO_ (for modes 3 and 4). The
LOAD input is provided to allow the user to load the
phase counters with the programming values to gener-
ate the correct LO phases. The input signals for mixing
are applied to the eight differential inputs, CWIN_+ and
CWIN_-. The summed I/Q baseband differential outputs
are provided on CW_IOUT+/- and CW_QOUT+/-.
CW_M1 and CW_M2 are used to select one of the four
possible modes of operation. See Table 1.
The serial interface is designed to allow multiple
devices to be easily daisy chained in order to minimize
program interface wiring. DOUT is available for this
daisy-chain function.
Programming the Beamformer
During normal CWD operation, the mixer clock at LO_ or
LO_LVDS+/- is on and the programming signals on DIN,
CLK, and LOAD are off. (LOAD = high, CLK = low, and
DIN = don’t care, but fixed to a high or low). To start the
programming sequence, turn off the mixer clock. Data is
shifted into the shift register at a recommended 10MHz
programming rate or 100ns minimum data clock
period/time. See Figure 5 for timing details.
After the shift registers are programmed, pull the LOAD
bus to logic-low and then back to logic-high to load the
internal counters into I/Q phase divider/selectors with
the proper values. LOAD must remain low for a mini-
mum time of tCLH. The user turns on the mixer clock to
start beamforming. The clock must turn on such that it
starts at the beginning of a mixer clock cycle.
DIN
CLK
LOAD
tDCLKPWH
DCLKPWL
tLD
tCLH
tDCLK
tDSU tHLD
tLDMIXCLK
MIXER
CLOCK ON
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK OFF
MIXER
CLOCK ON
Figure 5. Shift Register Timing Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX2038EVKIT | 制造商:Maxim Integrated Products 功能描述:ULTRASOUND VARIABLE-GAIN AMPLIFIER WITH CWD (12B COMPATIBLE - Boxed Product (Development Kits) |
| MAX2038混頻器 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| MAX2039 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Evaluation Kit |
| MAX2039_1 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Evaluation Kit |
| MAX2039ETP | 功能描述:射頻混合器 1.7GHz-2.2GHz Up/Down Mixer RoHS:否 制造商:NXP Semiconductors 頻率范圍: 轉換損失——最大: 工作電源電壓:6 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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