參數(shù)資料
型號(hào): MAX19713
廠商: Maxim Integrated Products, Inc.
英文描述: 10-Bit, 45Msps, Full-Duplex Analog Front-End
中文描述: 10位、45Msps、全雙工模擬前端
文件頁數(shù): 9/37頁
文件大?。?/td> 892K
代理商: MAX19713
M
10-Bit, 45Msps, Full-Duplex
Analog Front-End
_______________________________________________________________________________________
9
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33μF, C
L
< 5pF on all aux-DAC outputs, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Note 1:
Specifications from T
A
= +25°C to +85°C guaranteed by production tests. Specifications at T
A
< +25°C guaranteed by
design and characterization.
Note 2:
The minimum clock frequency (f
CLK
) for the MAX19713 is 7.5MHz (typ). The minimum aux-ADC sample rate clock frequency
(A
CLK
) is determined by f
CLK
and the chosen aux-ADC clock-divider value. The minimum aux-ADC A
CLK
> 7.5MHz / 128 =
58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-
version time (for no averaging, NAVG = 1) will be t
CONV
(max) = (12 x 1 x 128) / 7.5MHz = 205μs.
Note 3:
SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4:
Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tones.
Note 5:
Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
Note 6:
Guaranteed by design and characterization.
Typical Operating Characteristics
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
REFP
= C
REFN
= C
COM
= 0.33μF, T
A
= +25°C, unless otherwise noted.)
Rx ADC CHANNEL-IA FFT PLOT
(8192 SAMPLES)
M
FREQUENCY (MHz)
A
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
5
4
2
3
6
0
5
10
15
20
FUNDAMENTAL
f
IN
= 13.024292MHz
A
= -0.488dBFS
SINAD = 53.763dB
SNR = 54.003dB
SFDR = 71.6dBc
THD = -66.46dBc
Rx ADC CHANNEL-QA FFT PLOT
(
8
192 SAMPLES)
M
FREQUENCY (MHz)
A
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
5
4
2
3
6
FUNDAMENTAL
0
5
10
15
20
f
IN
= 13.024292MHz
A
= -0.48dBFS
SINAD = 54.216dB
SNR = 54.302dB
SFDR = 76dBc
THD = -71.311dBc
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOT
M
FREQUENCY (MHz)
A
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
f
IN1
= 1.7605591MHz
f
IN2
= 1.8484497MHz
A
IN1
= A
IN2
= -7dBFS
IMD = -65dBc
2f
IN1
- f
IN2
2f
IN2
- f
IN1
f
IN1
f
IN2
0
5
10
15
20
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