參數(shù)資料
型號: MAX19713
廠商: Maxim Integrated Products, Inc.
英文描述: 10-Bit, 45Msps, Full-Duplex Analog Front-End
中文描述: 10位、45Msps、全雙工模擬前端
文件頁數(shù): 18/37頁
文件大?。?/td> 892K
代理商: MAX19713
M
10-Bit, 45Msps, Full-Duplex
Analog Front-End
18
______________________________________________________________________________________
Figure 3. Rx ADC System Timing Diagram
t
DOQ
t
CL
t
CH
t
CLK
t
DOI
5 CLOCK-CYCLE LATENCY (IA)
5.5 CLOCK-CYCLE LATENCY (QA)
D0–D9
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
IA
QA
CLK
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode V
REFDAC
= 1.024V, External Reference Mode V
REFDAC
= V
REFIN
, V
FS
= 400 for 800mV
P-P
Full Scale)
The Tx DAC outputs (IDN, IDP, QDN, QDP) are biased at
an adjustable common-mode DC level and designed to
drive a differential input stage with
70k
Ω
input imped-
ance. This simplifies the analog interface between RF
quadrature upconverters and the MAX19713. Many RF
upconverters require a 0.71V to 1.06V common-mode
bias. The MAX19713 common-mode DC bias eliminates
discrete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC.
The Tx DAC differential analog outputs can-
not be used in single-ended mode because of the
internally generated common-mode DC level.
Table 2
shows the Tx DAC output voltage vs. input codes. Table
10 shows the selection of DC common-mode levels.
See Figure 4 for an illustration of the Tx DAC analog
output levels.
The Tx DAC also features an independent DC offset trim
on each ID–QD channel. This feature is configured
through the SPI interface. The DC offset correction is
used to optimize sideband and carrier suppression in the
Tx signal path (see Table 9).
DIFFERENTIAL OUTPUT VOLTAGE (V)
OFFSET BINARY (DA0–DA9)
INPUT DECIMAL CODE
11 1111 1111
1023
11 1111 1110
1022
10 0000 0001
513
10 0000 0000
512
01 1111 1111
511
00 0000 0001
1
00 0000 0000
0
V
V
FS
REFDAC
1024
1023
1023
(
)
×
V
V
FS
REFDAC
1024
1021
1023
(
)
×
V
V
FS
REFDAC
1024
3
1023
(
)
×
V
V
FS
REFDAC
1024
1
1023
(
)
×
V
V
FS
REFDAC
1024
1
1023
(
)
×
V
V
FS
REFDAC
1024
1021
1023
(
)
×
V
V
FS
REFDAC
1024
1023
1023
(
)
×
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