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參數(shù)資料
| 型號： | MAX1964TEEE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Tracking/Sequencing Triple/Quintuple Power-Supply Controllers |
| 中文描述： | 0.05 A SWITCHING CONTROLLER, 240 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, 0.025 INCH PITCH, QSOP-16 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 475K |
| 代理商： | MAX1964TEEE |
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current and load resistance, the total DC loop gain
(A
V(LDO)
) is approximately:
where V
T
is 26mV, and I
BIAS
is the current through the
base-to-emitter resistor (R
BE
). This bias resistor is typi-
cally 220
, providing approximately 3.2mA of bias cur-
rent.
The output capacitor creates the dominant pole.
However, the pass transistor
’
s input capacitance creates
a second pole in the system. Additionally, the output
capacitor
’
s ESR generate a zero, which may be used to
cancel the second pole if necessary. Therefore, in order
to achieve stable operation, use the following equations
to verify that the linear regulator is properly compensat-
ed:
1) First, determine the dominant pole set by the linear
regulator
’
s output capacitor and the load resistor:
unity-gain crossover = A
V(LDO)
POLE(CLDO)
2) Next, determine the second pole set by the base-to-
emitter capacitance (including the transistor
’
s input
capacitance), the transistor
’
s input resistance, and
the base-to-emitter pullup resistor:
3) A third pole is set by the linear regulator
’
s feedback
resistance and the capacitance between FB_ and
GND (including 20pF stray capacitance).
4) If the second and third pole occur well after unity-
gain crossover, the linear regulator will remain stable:
POLE(FB)
and
POLE(CBE) >
2
POLE(CLDO)
A
V(LDO)
However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with f
POLE(FB)
by changing
circuit components such that:
Do not use output capacitors with more than 200m
of
ESR. Typically, more output capacitance provides the
best solution, since this also reduces the output voltage
drop immediately after a load transient.
Linear Regulator Output Capacitors
Connect at least 1μF capacitor between the linear regu-
lator
’
s output and ground, as close to the MAX1964/
MAX1965 and external pass transistors as possible.
Depending on the selected pass transistor, larger
capacitor values may be required for stability (see
Stability Requirements
). Furthermore, the output capac-
itor
’
s equivalent series resistance (ESR) affects stability,
providing a zero that may be necessary to cancel the
second pole. Use output capacitors with an ESR less
than 200m
to ensure stability and optimum transient
response.
Once the minimum capacitor value for stability is deter-
mined, verify that the linear regulator
’
s output does not
contain excessive noise. Although adequate for stabili-
ty, small capacitor values may provide too much band-
width, making the linear regulator sensitive to noise.
Larger capacitor values reduce the bandwidth, thereby
reducing the regulator
’
s noise sensitivity.
For the negative linear regulator, if noise on the ground
reference causes the design to be marginally stable,
bypass the negative output back to its reference volt-
age (V
REF
, Figure 7). This technique reduces the differ-
ential noise on the output.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to sys-
tem noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or induc-
tively coupled EMI onto the base drive causes fluctua-
tions in the base current, which appear as noise on the
linear regulator
’
s output. Keep the base-drive traces
away from the step-down converter and as short as
possible to minimize noise coupling. Resistors in series
with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter
(Figure 5). Additionally, a bypass capacitor may be
placed across the base-to-emitter resistor (Figure 7).
This bypass capacitor, in addition to the transistor
’
s
input capacitance, could bring in a second pole that
will destabilize the linear regulator (see
Stability
Requirements
). Therefore, the stability requirements
determine the maximum base-to-emitter capacitance:
≈
POLE FB
OUT ESR
C
(
)
1
π
=
(
)
POLE FB
FB
C
1 2
(
)
1
2
π
=
(
)
=
+
POLE CBE
BE
C
π
BE
IN BJT
R
V h
BE LOAD
BE BE T FE
2
C
R
R
(
)
(
)
1
2
π
=
=
POLE CLDO
(
LDO LOAD
C
π
LOAD MAX
I
C
2
π
LDO LDO
)
(
)
1
2
A
V
I
I
V
V LDO
(
T
BIAS FE
LOAD
REF
)
.
≈
+
5 5
1
M
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________
23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX1965TEEP | Tracking/Sequencing Triple/Quintuple Power-Supply Controllers |
| MAX1966 | Low-Cost Voltage-Mode PWM Step-Down Controllers |
| MAX1967EUB | Low-Cost Voltage-Mode PWM Step-Down Controllers |
| MAX1966-MAX1967 | Low-Cost Voltage-Mode PWM Step-Down Controllers |
| MAX1966ESA | Low-Cost Voltage-Mode PWM Step-Down Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1964TEEE+ | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 Track/Seq Trpl/Wuint Power-Supply Ctlr RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| MAX1964TEEE+T | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 Track/Seq Trpl/Wuint Power-Supply Ctlr RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| MAX1964TEEE-T | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| MAX1965TEEP | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| MAX1965TEEP-T | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
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