
M
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
22
______________________________________________________________________________________
an internal 40k
pullup for about 4μs to see if the pin
voltage can be forced high (Figure 7). If the pin voltage
cannot be pulled to a logic high, the pin is considered
low impedance, and its impedance-mode logic state is
low. If the pin can be pulled to a logic high, the imped-
ance is considered high and so is the impedance-
mode logic state. Similarly, if the voltage level on the
pin is a logic high, an internal switch connects the pin
to an internal 8k
pulldown to see if the pin voltage can
be forced low. If so, the pin is high impedance, and its
impedance-mode logic state is high. In either sampling
condition, if the pin
’
s logic level does not change, the
pin is determined to be low impedance, and the imped-
ance-mode logic state is low.
A high pin impedance (logic high) is 100k
or greater,
and a low impedance (logic low) is 1k
or less. The
guaranteed levels for these impedances are 95k
and
1.05k
to allow the use of standard 100k
and 1k
resis-
tors with 5% tolerance.
Output Voltage Transition Timing (TIME)
The MAX1813 is designed to perform output voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC very suit-
able for IMVP-II CPUs and other CPUs that operate in
two or more modes with different core voltage levels.
The IMVP-II CPUs operate at multiple clock frequencies
and require multiple core voltages. When transitioning
*Float = no connection
Table 7. ZMODE Polarity Table
D0
D1
D2
D3
D4
CODE
ZMODE
ZMODE
MUX
S0/S1
DECODER
CODE
SEL0 SEL1
OUT
OUT
01 OR 10
IN
IMPEDANCE
DECODER
IN
OUT
00 OR 11
SUS MUX
SUS
OUT
DAC
1
0
S0
S1
SUS
D0-D4
DECODER
OUT
MAX1813
(FIGURE 7)
Figure 6. Internal Multiplexers Block Diagram
S1
GND
GND
GND
GND
REF
REF
REF
REF
Float*
Float*
Float*
Float*
V
CC
V
CC
V
CC
V
CC
S0
GND
REF
Float*
V
CC
GND
REF
Float*
V
CC
GND
REF
Float*
V
CC
GND
REF
Float*
V
CC
OUTPUT VOLTAGE (V)
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
Table 6. Suspend-Mode Output Voltages
CODE
0
0
1
1
ZMODE
0
1
0
1
Impedance Mode
Logic Mode
Logic Mode
Impedance Mode