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參數(shù)資料
| 型號： | MAX1608 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 16-Bit Bus Transceivers And Registers With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 八通道、SMBus至并行輸入/輸出擴展器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 291K |
| 代理商： | MAX1608 |
M
use the send-byte protocol. The shorter receive-byte
protocol can be used instead of the read-byte protocol,
provided the correct data register was previously
selected by a read-byte or write-byte instruction. Use
caution with the shorter protocols in multimaster sys-
tems, since a second master could overwrite the com-
mand byte without informing the first master. The
register selected at POR is 0b0000 0000 so that a
receive-byte transmission that occurs immediately after
initial power-up returns the setting of NDR1. SPOR
does not reset the register pointer.
Data Registers
The MAX1608/MAX1609 each have seven data regis-
ters, three normal registers, three suspend registers,
and one readback register. The
SMBUS
line deter-
mines which registers controls the output states and
the interrupt mask states (normal registers if
SUSBUS
=
1, suspend registers if
SMBSUS
= 0).
Registers 1 (NDR1 and SDR1) set the state of each of
the eight outputs to either low or high impedance.
When using an external pull-up, high impedance corre-
sponds to an output high. To use the IO_ pins as TTL
inputs only, set the corresponding bit high. The
MAX1608 powers up with all IO_ pins set low; the
MAX1609 powers up with all IO_ pins set to high
impedance (Table 3).
Register 2 (NDR2 and SDR2) are used to mask rising-
edge triggered interrupts, while Register 3 are used to
mask falling-edge triggered interrupts. On power-up, all
interrupts are masked (Tables 4 and 5).
The IO_ Status Data Register (RSB, Table 6) reads the
actual TTL-logic level of the IO_ pins. The IO_ pins are
sampled on the falling edge of the third byte’s acknowl-
edge (ACK) for a read-byte format, or on the falling
edge of the first byte’s ACK for a receive-byte protocol
(Figure 5). There is a 15μs data-setup time require-
ment, due to the slow level translators needed for high-
voltage (28V) operation. Data-hold time is 300ns. Do
not write to the RSB register because writes to read-
only registers are redirected to NDR1. SMBus sends
Octal SMBus-to-Parallel I/O Expanders
8
_______________________________________________________________________________________
1b
ACK
1b
7 bits
ADDRESS
ACK
1b
WR
8 bits
DATA
1b
ACK
P
8 bits
S
COMMAND
Write-Byte Format
Receive-Byte Format
Slave Address
Command Byte: selects
which register you are
writing to
Data Byte: data goes into the register
set by the command byte
1b
ACK
1b
7 bits
ADDRESS
ACK
1b
WR
S
1b
ACK
8 bits
DATA
7 bits
ADDRESS
1b
RD
1b
8 bits
///
P
S
COMMAND
Slave Address
Slave Address
Command Byte: sends command
with no data; usually used for one-
shot command
Command Byte: selects
which register you are
reading from
Slave Address: repeated
due to change in data-
flow direction
Data Byte: reads from
the register set by the
command byte
1b
ACK
7 bits
ADDRESS
1b
RD
8 bits
DATA
1b
///
P
S
Data Byte: reads data from
the register commanded
by the last read-byte or
write-byte transmission;
also used for SMBus Alert
Response return address
S = Start condition
P = Stop condition
Shaded = Slave transmission
Ack= Acknowledged = 0
/// = Not acknowledged = 1
WR = Write = 0
RD = Read =1
Figure 2. SMBus Protocols
1b
ACK
7 bits
ADDRESS
1b
WR
8 bits
COMMAND
1b
ACK
P
S
Send-Byte Format
Read-Byte Format
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| MAX1609EEE | Octal SMBus-to-Parallel I/O Expanders |
| MAX1608EEE | 16-Bit Bus Transceivers And Registers With 3-State Outputs 56-SSOP -40 to 85 |
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