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參數(shù)資料
| 型號： | MAX1608 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 16-Bit Bus Transceivers And Registers With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 八通道、SMBus至并行輸入/輸出擴展器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 291K |
| 代理商： | MAX1608 |
M
configurations asynchronously, eliminating latencies
introduced by the serial bus.
ALERT
The MAX1608/MAX1609 can generate hardware inter-
rupts whenever the logic states of the IO_ pins change
or when thermal shutdown occurs. Interrupts are sig-
naled on the
ALERT
pin. The IO_ interrupts can be
masked individually through the mask registers.
Registers NDR2 and SDR2 mask the IO_ rising-edge
interrupts, while NDR3 and SDR3 mask the IO_ falling-
edge interrupts. The power-on-reset state masks all
interrupts (Tables 4 and 5).
The thermal-shutdown protection also generates an
interrupt. This interrupt cannot be masked (see
Thermal
Shutdown
section). An interrupt can be cleared with a
SPOR or an Alert Response. However, after an interrupt
has occurred, masking will not clear it.
Alert Response Address (0b00011001)
The alert response (interrupt pointer) address provides
quick fault identification for simple slave devices that
cannot initiate communication as a bus master. When a
slave device generates an interrupt, the host (bus mas-
ter) interrogates the bus slave devices through a special
receive-byte operation that includes the alert response
address (0x19). The offending slave device returns its
own address during this receive-byte operation.
The interrupt pointer address can activate several dif-
ferent slave devices simultaneously. If more than one
Octal SMBus-to-Parallel I/O Expanders
10
______________________________________________________________________________________
Figure 5. Registers/IO_ Update Timing Diagram
t
DH:DAT
SCL
SDA
IO_
t
DH:DAT
t
SCL:IO
STOP
REGISTERS
UPDATED*
ACKNOWLEDGE
BIT CLOCKED
INTO MASTER
LAST BIT
CLOCKED
INTO SLAVE**
*NDR#, SDR# ARE LOADED. RAP, SPOR ARE INITIATED. RSB IS SAMPLED.
**DURING A RECEIVE-BYTE PROTOCOL, CORRESPONDS TO THE R/W BIT. DURING A
READ/WRITE-BYTE PROTOCOL, CORRESPONDS TO LAST BIT OF DATA.
SLAVE PULLING
SDA LOW
IO_TRANSITION
NDR2
01h
1111 1111
NDR3
02h
1111 1111
SDR1
03h
0000 0000
SDR2
04h
1111 1111
RAP
07h
—
COMMAND
POR STATE
REGISTER
RSB
06h
—
SDR3
05h
1111 1111
00h
0000 0000
NDR1
08h
MAX1608
—
MAX1609
—
1111 1111
1111 1111
1111 1111
1111 1111
SPOR
—
1111 1111
1111 1111
Sample the address pins.
Normal Data Register 2. Masks the L/H interrupt.
Normal Data Register 3. Masks the H/L interrupt.
Suspend Data Register 1. Sets the IO_ states.
Suspend Data Register 2. Masks the L/H interrupt.
IO_ Status Data Register. Read pin state.
Suspend Data Register 3. Masks the H/L interrupt.
Normal Data Register 1. Sets the IO_ states.
FUNCTION
FEh
4Dh
MFID
—
4Dh
Execute software POR and samples address pins.
Read manufacturer ID (ASCII code for "M"axim).
Table 2. Command-Byte/Register Assignment
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