參數(shù)資料
型號(hào): MAX16049ATN+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC56
封裝: 8 X 8 MM, ROHS COMPLIANT, TQFN-56
文件頁數(shù): 46/61頁
文件大?。?/td> 790K
代理商: MAX16049ATN+
MAX16047A/MAX16049A
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
50
______________________________________________________________________________________
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 14 for a diagram of the finite state
machine. The possible states are described below:
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally. This state can be reached
from any state by driving TMS high for five clock cycles.
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Capture-DR: Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the select-
ed test data register does not allow parallel loads, the
test data register remains at its current value. On the
rising edge of TCK, the controller goes to the shift-DR
state if TMS is low or it goes to the exit1-DR state if TMS
is high.
TEST-LOGIC-RESET
1
11
0
RUN-TEST/IDLE
0
1
0
1
0
1
0
1
0
1
SELECT-DR-SCAN
SELECT-IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR
PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR
UPDATE-IR
0
1
0
1
Figure 14. TAP Controller State Diagram
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