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參數(shù)資料
| 型號： | MAX159BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 108KSPS 8-UMAX |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.7mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin MAX
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1F capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1F capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX159 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300Vp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) - VFS(5.25V).
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
05
SCLK Clock Frequency
fSCLK
0.1
2.17
MHz
SCLK Fall to Output Data Valid
tDO
20
120
ns
215
CS/SHDN Fall to Output Enable
Wake-Up Time
tWAKE
2.5
s
tDV
120
ns
CS/SHDN Rise to Output
Disable
tTR
120
ns
SCLK Pulse Width High
tCH
50
ns
CONDITIONS
Internal clock, SCLK for data transfer only
(Note 8)
Internal clock, SCLK for data transfer only
External clock
CL = 100pF
External clock
CL = 100pF (Figure 1)
ns
SCLK to CS/SHDN Setup
tSCLKS
60
CS/SHDN Pulse Width
tCS
60
ns
215
SCLK Pulse Width Low
tCL
50
ns
Internal clock, SCLK for data transfer only
(Note 8)
External clock
POWER REQUIREMENTS
Power-Supply Rejection
(Note 9)
PSR
±0.15
mV
VDD = 2.7V to 5.25V, full-scale input
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Positive Supply Voltage
VDD
+2.7
+5.25
V
CONDITIONS
Positive Supply Current
IDD
0.9
2.0
mA
Operating mode
Positive Supply Current
IDD
0.2
5
A
Shutdown, CS/SHDN = GND
POWER REQUIREMENTS
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