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參數(shù)資料
| 型號： | MAX157BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 108KSPS 2CH 8-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極 |
star-point (Figure 11) connecting the two ground sys-
tems (analog and digital). For lowest-noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass VDD to the star ground with a network
of two parallel capacitors, 0.1F and 1F, located as
close as possible to the power supply pin of the
MAX157/MAX159. Minimize capacitor lead length for
best supply-noise rejection and add an attenuation
resistor (10
) if the power supply is extremely noisy.
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin MAX
______________________________________________________________________________________
13
SCK
SDI
GND
I/O
SCLK
DOUT
CS/SHDN
VDD
MAX157
MAX159
PIC16/PIC17
CHID
D9
D8
D7
D6
1
2
3
4
5
6
7
8
9
10
11
121314
15
16
D5
D4
D3
D2
D1
HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ
2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
MSB
LSB
D0
S1
S0
Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
CHID
D9
D8
D7
D6
1
2
3
4
5
6
7
8
9
10
11
121314
15
16
D5
D4
D3
D2
D1
HIGH-Z
DOUT
CS/SHDN
SCLK
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
MSB
LSB
D0
S1
S0
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
+3V
GND
+3V
POWER SUPPLIES
DGND
+3V
GND
VDD
DIGITAL
CIRCUITRY
MAX157
MAX159
R* = 10
1
F
0.1
F
* OPTIONAL FILTER RESISTOR
Figure 11. Power-Supply Bypassing and Grounding
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