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參數(shù)資料
| 型號： | MAX157BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 108KSPS 2CH 8-UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin MAX
10
______________________________________________________________________________________
Output Data Format
Table 1 illustrates the 16-bit, serial data-stream output
format for both the MAX157 and MAX159. The first three
bits are always logic high (including the EOC bit for
internal clock mode), followed by the channel identifica-
tion (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for
MAX159), the 10 bits of data in MSB first format, and
two sub-LSB bits (S1 and S0). After the last bit has been
read out, additional SCLK pulses will clock out trailing
zeros. DOUT transitions on the falling edge of SCLK.
The output remains high impedance when CS/SHDN is
high.
External Reference
An external reference is required for both the MAX157
and MAX159. At REF, the DC input resistance is a mini-
mum of 18k
. During a conversion, a reference must
be able to deliver 250A of DC load current and have
an output impedance of 10
or less. Use a 0.1F
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to (VDD +
50mV) although noise levels will decrease effective res-
olution at lower reference voltages.
Automatic Power-Down Mode
Whenever the MAX157/MAX159 are not selected
(CS/SHDN = VDD), the parts enter their shutdown mode.
In shutdown all internal circuitry is turned off, which
reduces the supply current to typically less than 0.2A.
With an external reference stable to within 1LSB, the
wake-up time is 2.5s. If the external reference is not sta-
ble within 1LSB, the wake-up time must be increased to
allow the reference to stabilize.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
SNR(MAX) = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
DOUT
D7
D8
MSB
CHID
SAMPLING INSTANT
HIGH-Z
D6
D5
D4
D3
D2
D1
D0
S1
S0
HIGH-Z
SCLK
678
9
10
11
12
3
4
5
12
13
14
15
16
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE
CS/SHDN
Figure 6. External Clock Mode Timing
CS/SHDN
SCLK
DOUT
tCL
tDV
HIGH-Z
tCH
tCS
tDO
tTR
tSCLKS
Figure 7. Detailed Serial-Interface Timing Sequence
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