參數(shù)資料
      型號: MAX14830ETM+
      廠商: Maxim Integrated Products
      文件頁數(shù): 13/68頁
      文件大?。?/td> 0K
      描述: SEMICONDUCTOR OTHER
      標準包裝: 43
      系列: *
      20
      Maxim Integrated
      Quad Serial UART with 128-Word FIFOs
      MAX14830
      The receiver can be turned off through MODE1[0]:
      RxDisabl. When this bit is set to 1, the MAX14830 turns
      the receiver off immediately following the current word
      and does not receive any further data.
      The RX_ input logic can be inverted through IrDA[4]:
      RxInv.
      Line Noise Indication
      When operating in standard or 2x (i.e. not 4x) rate mode,
      the MAX14830 checks that the binary logic level of the
      three samples per received bit are identical. If any of
      the three samples have differing logic levels, then noise
      on the transmission line has affected the received data
      and is considered to be noisy. This noise indication is
      reflected in the LSR[5]: RxNoise bit for each received
      byte. Parity errors are another indication of noise, but are
      not as sensitive.
      Clocking and Baud-Rate Generation
      The MAX14830 can be clocked by an external crystal,
      or an external clock source. Figure 7 shows a simplified
      diagram of the clocking circuitry. When the MAX14830
      is clocked by a crystal, the STSInt[5]: ClockReady indi-
      cates when the clocks have settled and the baud-rate
      generator is ready for stable operation.
      Each UART baud rate can be individually programmed.
      To achieve fast baud rate changes, first disable the
      UART's clock by setting CLKDisabl to 1. Then change
      the baud rate divisor and subsequently enable the clock
      via CLKDisabl.
      To check that the UART's clocking is programmed as
      expected, route the baud rate clock to RTS using the
      CLKtoRTS bit. The clock rate of this is 16x the baud rate
      in standard operating mode and 8x the baud rate in 2x
      rate mode. In 4x rate mode, the CLKOUT frequency is
      4x the programmed baud rate. If the fractional portion of
      the baud-rate generator is used, the clock is not regular
      and exhibits jitter.
      Crystal Oscillator
      Set BRGConfig[6]: CLKDisabl to 0 and CLKSource[1]:
      CrystalEn to 1 to enable and select the crystal oscil-
      lator. The on-chip crystal oscillator circuit has load
      capacitances of 16pF (typ) integrated in both XIN and
      XOUT. Connect an external crystal or ceramic oscillator
      between XIN and XOUT.
      External Clock Source
      Connect an external clock source to XIN when not using
      a crystal oscillator. Leave XOUT unconnected. Set
      CLKSource[1]: CrystalEn to 0 to select external clocking.
      PLL and Predivider
      The internal predivider and PLL allow for a wide range of
      external clock frequencies and baud rates. The PLL can
      be configured to multiply the input clock rate by a factor
      of 6, 48, 96, or 144 through the PLLConfig register. The
      predivider, located between the input clock and the PLL,
      allows division of the input clock by a factor between 1
      and 63 by writing to PLLConfig[5:0]. See the PLLConfig
      register description for more information.
      Figure 7. Clock Selection Diagram
      PLLBypass
      CrystalEn
      XOUT
      CRYSTAL
      OSCILLATOR
      PLLEn
      ClkDisabl[0...3]
      XIN
      DIVIDER
      PLL
      FRACTIONAL
      BAUD RATE
      GENERATOR 1
      FRACTIONAL
      BAUD RATE
      GENERATOR 2
      FRACTIONAL
      BAUD RATE
      GENERATOR 3
      FRACTIONAL
      BAUD RATE
      GENERATOR 0
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