參數(shù)資料
型號: MAX14830ETM+
廠商: Maxim Integrated Products
文件頁數(shù): 48/68頁
文件大?。?/td> 0K
描述: SEMICONDUCTOR OTHER
標準包裝: 43
系列: *
52
Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
BRGConfig—Baud-Rate Generator Configuration Register
Bit 7: No Function
Bit 6: CLKDisabl
Set the CLKDisabl bit high to disable internal clocking of the UART. This is useful to achieve fast baud rate reprogram-
ming or to reduce power dissipation when a specific UART channel is not used. Set CLKDisabl low for normal UART
operation.
Bit 5: 4xMode
When the 4xMode bit is set high, the MAX14830 baud rate is quadruple the regular (16x sampling) baud rate. The
2xMode bit should be set low if 4xMode is enabled. See the 2x and 4x Rate Modes section for more information.
Bit 4: 2xMode
When the 2xMode bit is set high, the MAX14830 baud rate is double the regular (16x sampling) baud rate. See the 2x
and 4x Rate Modes section for a detailed description.
Bits 3–0: FRACT[n]
This is the fractional portion of the baud-rate generator divisor. Set FRACT[n] to zero if not used. See the Fractional
Baud-Rate Generator section for calculations.
DIVLSB—Baud-Rate Generator LSB Divisor Register
DIVLSB and DIVMSB define the baud-rate generator integer divisors. The minimum value is 1. See the Fractional Baud-
Rate Generator section for more information.
Bits 7–0: Div[n]
The DIVLSB register is the LSBs of the integer divisor portion (DIV) of the baud-rate generator.
DIVMSB—Baud-Rate Generator MSB Divisor Register
Bits 7–0: Div[n]
The DIVMSB register is the MSB portion of the integer divisor (DIV).
ADDRESS:
0x1B
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
CLKDisabl
4xMode
2xMode
FRACT3
FRACT2
FRACT1
FRACT0
RESET
0
ADDRESS:
0x1C
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Div7
Div6
Div5
Div4
Div3
Div2
Div1
Div0
RESET
0
1
ADDRESS:
0x1D
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Div15
Div14
Div13
Div12
Div11
Div10
Div9
Div8
RESET
0
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