參數(shù)資料
型號： MAX1464AAI+T
廠商： Maxim Integrated Products
文件頁數(shù)： 19/47頁
文件大?。?/td> 0K
描述： IC SENSOR SIGNAL COND 28-SSOP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,000
類型： 信號調(diào)節(jié)器
輸入類型： 模擬
輸出類型： 邏輯
接口： SPI
電流 - 電源： 890µA
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應商設備封裝： 28-SSOP
包裝： 帶卷 (TR)
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
26
Maxim Integrated
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from port-X to the A-
register.
The port-X contents are unchanged.
The previous contents of A-register are overwritten
and lost.
The port-X can be any of the CPU ports.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
WRX
Write Port X
Op-code:
1110 XXXXBINARY EXh
Operation:
Port-X
← A-register
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from the A-register to
port-X.
The A-register contents are unchanged.
The previous contents of port-X are overwritten
and lost.
The port-X can be any of the CPU ports.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
MLT
Multiply
Op-code:
1111 0011BINARY F3h
Operation:
A-register | M-register
← N-register x M-register
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
16 cycles
Description:
Perform a 16-bit by 16-bit arithmetic multiplication of
the M-register and the N-register producing a 32-bit
result. The 32-bit result is stored in two 16-bit registers;
the A-register receives the most significant word of the
result and the M-register receives the least significant
word of the result.
The A-register must be cleared to zero (CLX A) before
executing the MLT instruction. The previous contents of
the A-register are overwritten and lost.
The previous contents of the M-register are overwritten
and lost.
The contents of the N-register are not altered.
The register op code must be 3h.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
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