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參數(shù)資料
| 型號(hào)： | MAX145BMJA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MAX145BMJA |
ns
M
+2.7V, Low-Power, 2-Channel, 108ksps,
S erial 12-Bit ADCs in 8-Pin μMAX
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Figure 7)
(V
DD
= +2.7V to +5.25V, V
REF
= 2.5V, 0.1μF capacitor at REF, f
SCLK
= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
CONDITIONS
t
WAKE
Wake-Up Time (Note 10)
CS
/SHDN Fall to Output Enable
Internal clock, SCLK for data transfer only
(Note 8)
External clock
Internal clock, SCLK for data transfer only
C
L
= 100pF, Figure 1
C
L
= 100pF, Figure 1
External clock
External clock
C
L
= 100pF
50
ns
215
t
CH
0
5
SCLK Pulse Width High
ns
215
t
CL
SCLK Pulse Width Low
ns
ns
120
120
2.17
t
TR
t
DO
CS
/SHDN Rise to Output Disable
SCLK Fall to Output Data Valid
ns
120
t
DV
μs
2.5
20
0.1
MHz
f
SCLK
SCLK Clock Frequency
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
ns
60
60
t
SCLKS
t
CS
SCLK to
CS
/SHDN Setup
CS
/SHDN Pulse Width
Note 1:
Note 2:
Tested at V
DD
= +2.7V.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Offset nulled.
“On” channel is grounded; sine wave applied to “off” channel (MAX144 only).
Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
The common-mode range for the analog inputs is from GND to V
DD
(MAX145 only).
ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Guaranteed by design. Not subject to production testing.
Measured as V
FS(2.7V)
- V
FS(5.25V)
.
Note 10:
SCLK must remain stable during this time.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
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