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參數(shù)資料
| 型號(hào)： | MAX1450EAP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Low-Cost, 1%-Accurate Signal Conditioner for Piezoresistive Sensors |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | 5.30 X 0.65 MM, SSOP-20 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | MAX1450EAP |
______________ Detailed Desc ription
Analog S ignal Path
The MAX1450’s signal path is fully differential and com-
bines the following three stages: a 3-bit PGA with
selectable gains of 39, 65, 91, 117, 143, 169, 195, and
221; a summing junction; and a differential to single-
ended output buffer (Figure 1).
Programmable-Gain Amplifier
The analog signal is first fed into a programmable-gain
instrumentation amplifier with a CMRR of 90dB and a
common-mode input range from V
SS
to V
DD
. Pins A0,
A1, and A2 set the PGA gain anywhere from 39V/V to
221V/V (in steps of 26).
M
Low-Cost, 1%-Ac c urate S ignal Conditioner
for Piezoresistive S ensors
4
_______________________________________________________________________________________
NAME
FUNCTION
1
INP
Positive Sensor Input. Input impedance is typically 1M
. Rail-to-rail input range.
PIN
2, 3,
12, 16
I.C.
Internally connected. Leave unconnected.
4
SOTC
Offset TC Sign Bit Input. A logic low inverts V
OFFTC
with respect to V
SS.
This pin is internally pulled to V
SS
via a 1M
(typical) resistor. Connect to V
DD
to add V
OFFTC
to the PGA output, or leave unconnected (or
connect to V
SS
) to subtract V
OFFTC
from the PGA output.
Offset Sign Bit Input. A logic low inverts V
OFFSET
with respect to V
SS
. This pin is internally pulled to V
SS
via
a 1M
(typical) resistor. Connect to V
DD
to add V
OFFSET
to the PGA output, or leave unconnected (or con-
nect to V
SS
) to subtract V
OFFSET
from the PGA output.
8
OFFTC
Offset TC Adjust. Analog input summed with PGA output and V
OFFSET
. Input impedance is typically 1M
.
Rail-to-rail input range.
7
A0
PGA Gain-Set LSB Input. Internally pulled to V
SS
via a 1M
(typical) resistor. Connect to V
DD
for a logic
high or V
SS
for a logic low.
6
A1
PGA Gain-Set Input. Internally pulled to V
SS
via a 1M
(typical) resistor. Connect to V
DD
for a logic high or
V
SS
for a logic low.
5
SOFF
14
OUT
PGA Output Voltage. Connect a 0.1μF capacitor from OUT to V
SS
.
Positive Supply Voltage Input. Connect a 0.1μF capacitor from V
DD
to V
SS
.
Current-Source Reference. Connect a 50k
(typical) resistor from ISRC to V
SS
.
13
A2
PGA Gain-Set MSB Input. Internally pulled to V
SS
via a 11k
(typical) resistor. Connect to V
DD
for a logic
high or V
SS
for a logic low.
11
FSOTRIM
Bridge Drive Current-Set Input. The voltage on this pin sets the nominal I
ISRC
. See the Bridge Drive section.
10
BBUF
Buffered Bridge-Voltage Output (the voltage at BDRIVE). Use with correction resistor R
STC
to correct for FSO
tempco.
9
OFFSET
Offset Adjust Input. Analog input summed with PGA output and V
OFFTC
. Input impedance is typically
1M
. Rail-to-rail input range.
Pin Desc ription
15
V
DD
ISRC
20
INM
Negative Sensor Input. Input impedance is typically 1M
. Rail-to-rail input range.
19
V
SS
Negative Power-Supply Input.
18
BDRIVE
Sensor Excitation Current Output. This pin drives a nominal 0.5mA through the bridge.
17
OFFTC SOTC
OFFSET SOFF
±
±
A2
INP
INM
A1 A0
PGA
Σ
A = 1
OUT
Figure 1. Signal-Path Functional Diagram
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