參數(shù)資料
型號: MAX1426EAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/16頁
文件大?。?/td> 0K
描述: IC ADC 10BITS 10MSPS 28SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 10
采樣率(每秒): 10M
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 210mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
MAX1426
10-Bit, 10Msps ADC
______________________________________________________________________________________
13
octal D-latched flip-flop (74ALS374), or use octal
buffers such as the 74ALS541.
Typical Application Using an
External Reference
Figure 7 shows an application circuit that shuts down
the internal reference, allowing an external reference to
be used for selecting a different common-mode volt-
age. This added flexibility also allows for ratiometric
conversions, as well as for calibration.
Using Transformer Coupling
A small transformer (Figure 8) provides isolation and
AC-coupling to the ADC’s input. Connecting the trans-
former's center tap to CML provides a +2.25VDC level
shift to the input. Transformer coupling reduces the
need for high-speed op amps, thereby reducing cost.
Although a 1:1 transformer is shown, a step-up trans-
former may be selected to reduce the drive require-
ments.
Single-Ended DC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. The MAX4106 quad op amp provides high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
4.5k
CMLP
INP
INN
CMLN
4.5k
TO T/H INPUT
5.5k
Figure 6. Analog Input DC Bias Circuit
Figure 7. Using an External Reference for REFP, REFN, and CML (internal reference shut down)
MAX1426
REFIN
REFN
R
50
R
+1V
R
50
50
R
VDD
2
CML
0.1
F
0.1
F
0.1
F
AGND
VDD
2
VDD
2
VDD
4
VDD
4
MAX4284
( )
VDD
2
- 1V
(
)
REFP
VDD
2
+ 1V
(
)
MAX4284
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