參數(shù)資料
型號(hào): MAX1422CCM+TD
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/15頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 20MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 152mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,雙極
log portion of the MAX1421, thereby degrading its
dynamic performance. The use of digital buffers (e.g.
74LVCH16244) on the digital outputs of the ADCs can
further isolate the digital outputs from heavy capacitive
loads. To further improve the MAX1422 dynamic perfor-
mance, add small 100
series resistors to the digital
output paths, close to the ADC. Figure 5 displays the
timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1422
samples the analog input signal on the rising edge of
CLK (falling edge of CLK). and output data is valid
seven clock cycles (latency) later. Figure 6 also dis-
plays the relationship between the input clock parame-
ters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AVDD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associ-
ated with high-speed op amps. Select the RISO and
CIN values to optimize the filter performance and to suit
a particular application. For the application in Figure 7,
a RISO of 50
is placed before the capacitive load to
prevent ringing and oscillation. The 22pF CIN capacitor
acts as a small bypassing capacitor.Connecting CIN
from INN to INP may further improve dynamic perfor-
mance.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully dif-
ferential signal, required by the MAX1422 for optimum
performance. Connecting the center tap of the trans-
former to CML provides an AVDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1422 provides better SFDR and
THD with fully differential input signals over single-
ended input signals, especially for very high input fre-
quencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to single-
ended mode.
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
______________________________________________________________________________________
11
D11–D0
10k
10k
10k
10k
AVDD
ADC
CLK
INN
INP
AGND
MAX1422
Figure 4. Simplified Clock Input Circuit
OUTPUT
DATA D11–D0
OE
tBD
tBE
HIGH-Z
VALID DATA
Figure 5. Output Enable Timing
DIFFERENTIAL
INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET BINARY
VREF
2047/2048
+FULL SCALE -
1LSB
1111 1111 1111
VREF
2046/2048
+FULL SCALE -
2LSB
1111 1111 1110
VREF 1/2048
+1 LSB
1000 0000 0001
0
Bipolar Zero
1000 0000 0000
-VREF 1/2048
-1 LSB
0111 1111 1111
-VREF
2046/2048
-FULL SCALE
+1 LSB
0000 0000 0001
-VREF
2047/2048
-FULL SCALE
0000 0000 0000
Table 1. MAX1422 Output Code For
Differential Inputs
*VREF = VREFP - VREFN
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MAX1422ECM-D 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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