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參數(shù)資料
| 型號： | MAX1422CCM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 20MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 152mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
MAX1422
Detailed Description
The MAX1422 uses a 12-stage, fully differential,
pipelined architecture (Figure 1), that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Including the delay through the
output latch, the latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the held-
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two and the product is
passed along to the next pipeline stage. This process
is repeated until the signal has been processed by all
12 stages. Each stage provides a 1-bit resolution.
Digital error correction compensates for ADC compara-
tor offsets in each pipeline stage and ensures no
missing codes.
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
8
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8, 9,
12, 13, 16,
19, 41, 48
AGND
Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10, 11,
14, 15, 20,
42, 47
AVDD
Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel
combination of a 0.1F, and a 1nF capacitor. Connect a single 10F and 1F capacitor combination
between AVDD and AGND.
6
INP
Positive Analog Signal Input
7
INN
Negative Analog Signal Input
17
CLK
Clock Frequency Input. Clock frequency input ranges from 100kHz to 20MHz.
18
CLK
Complementary Clock Frequency Input. This input is used for differential clock input. If the ADC is
driven with a single-ended clock, bypass CLK with 0.1F capacitor to AGND.
21, 31, 32
DVDD
Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel
combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination
between DVDD and DGND.
22, 29, 30
DGND
Digital Ground
23–28
D0–D5
Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
33–38
D6–D11
Digital Data Outputs. D6 through D11, where D11 represents the MSB.
39
OE
Output Enable Input. A logic "1" on OE places the outputs D0–D11 into a high-impedance state. A
logic "0" allows for the data bits to be read from the outputs.
40
PD
Shutdown Input. A logic "1" on PD places the ADC into shutdown mode.
43
REFIN
External Reference Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
44
REFP
Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFP should be biased toVCML + VDIFF/2.
45
REFN
Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with
1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to
VCML - VDIFF/2.
46
CML
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with
1nF. With the internal reference disabled (REFIN = AGND), CML accepts an external voltage of
1.65V ±10%.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1422ECM | 制造商:Maxim Integrated Products 功能描述:48 PINS TQFP PKG - Bulk |
| MAX1422ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1422ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1422ECM-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1422ECM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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