- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2008 > MAX1421CCM+D (Maxim Integrated Products)IC ADC 12BIT 40MSPS 48LQFP PDF資料下載
參數(shù)資料
| 型號： | MAX1421CCM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 40MSPS 48LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 214mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
12
______________________________________________________________________________________
Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10k
resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1421 clock input.
Output Enable (
O
OE
E), Power-Down (PD), and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down. All
data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS-logic compatible. There is a seven clock-
cycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (
≤ 10pF), to avoid
large digital currents that could feed back into the analog
portion of the MAX1421, thereby degrading its dynamic
performance. The use of digital
buffers (e.g.,
74LVCH16244) on the digital outputs of the ADC can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1421, add small-series resistors of 100
to the
digital output paths, close to the ADC. Figure 5 displays
the timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1421
samples at the rising edge of CLK (falling edge of CLK)
and output data is valid seven clock cycles (latency)
later. Figure 6 also displays the relationship between
the input clock parameters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AVDD / 2 output voltage for level-
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associat-
ed with high-speed op amps. Select the RISO and CIN
values to optimize the filter performance and to suit a
particular application. For the application in Figure 7, a
RISO of 50
is placed before the capacitive load to pre-
vent ringing and oscillation. The 22pF CIN capacitor
acts as a small bypassing capacitor.
Connecting CIN from INN to INP may further improve
dynamic performance.
D11–D0
10k
10k
10k
10k
AVDD
ADC
CLK
INN
INP
AGND
MAX1421
Figure 4. Simplified Clock Input Circuit
OUTPUT
DATA D11–D0
OE
tBD
tBE
HIGH-Z
VALID DATA
Figure 5. Output Enable Timing
Table 1. MAX1421 Output Code for
Differential Inputs
DIFFERENTIAL
INPUT VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET
BINARY
VREF
× 2047/2048
+FULL SCALE -
1LSB
1111 1111 1111
VREF
× 2046/2048
+FULL SCALE -
2LSB
1111 1111 1110
VREF
× 1/2048
+ 1 LSB
1000 0000 0001
0
Bipolar Zero
1000 0000 0000
-VREF
× 1/2048
- 1 LSB
0111 1111 1111
-VREF
× 2046/2048
-FULL SCALE +
1 LSB
0000 0000 0001
-VREF
× 2047/2048
-FULL SCALE
0000 0000 0000
*VREF = VREFP - VREFN
相關PDF資料 |
PDF描述 |
|---|---|
| MAX1426EAI+T | IC ADC 10BITS 10MSPS 28SSOP |
| MAX1434ECQ+D | IC ADC 10BIT 50MSPS 100-TQFP |
| MAX1444EHJ+T | IC ADC 10BIT 40MSPS 32-TQFP |
| MAX1499ECJ+ | IC ADC 3 1/2DIG W/LED DVR 32TQFP |
| MAX152EPP+ | IC ADC 8BIT 1UA PWR-DWN 20-DIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1421CCM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1421ECM | 制造商:Maxim Integrated Products 功能描述:48 PINS TQFP PKG - Bulk |
| MAX1421ECM+ | 制造商:Maxim Integrated Products 功能描述:IC ADC LOW POWER 12BIT 3.3V SMD |
| MAX1421ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1421ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。