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參數(shù)資料
| 型號： | MAX1421CCM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 40MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 214mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
______________________________________________________________________________________
11
The MAX1421 provides three modes of reference oper-
ation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22F, in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK,
C
CL
LK
K)
The MAX1421’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1F
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
where fIN represents the analog input frequency and
tAJ is the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AVDD / 2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
S
1
2t
dB
IN
AJ
NR
=×
××
20
10
log
π
MAX1421
REFIN
REFN
R
50
R
+1V
R
50
50
R
AVDD
CML
1nF
0.22
F
1nF
0.22
F
1nF
0.22
F
AGND
AVDD
2
AVDD
4
MAX4284
( )
REFP
+ 1V
(
)
AVDD
2
+ 1V
(
)
AVDD
2
AVDD
2
AVDD
4
AVDD
2
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
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| MAX1421CCM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| MAX1421ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1421ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 40Msps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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