參數(shù)資料
型號： MAX1403EVKIT
廠商： Maxim Integrated Products
文件頁數(shù)： 7/36頁
文件大小： 0K
描述： EVAL KIT FOR MAX1403
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 18
采樣率（每秒）： 480
數(shù)據(jù)接口： 串行
輸入范圍： ±VREF/增益
在以下條件下的電源（標準）： 16.9mW @ 480SPS
工作溫度： 0°C ~ 70°C
已用 IC / 零件： MAX1403
已供物品： 板，CD
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
15
Selecting Clock Polarity
The serial interface can be operated with the clock idling
either high or low. This is compatible with Motorola’s SPI
interface operated in CPOL = 1, CPHA = 1 mode or
CPOL = 0, CPHA = 1 mode. The clock polarity is deter-
mined by the state of SCLK at the falling edge of CS.
Ensure that the setup times t4/t12 and t5/t13 are not violat-
ed. If CS is connected to ground, resulting in no falling
edge on CS, SCLK must idle high (CPOL = 1, CPHA = 1).
Data-Ready Signal (DRDY bit true or IIN
NTT = low)
The data-ready signal indicates that new data may be
read from the 24-bit data register. After the end of a suc-
cessful data register read, the data-ready signal
becomes false. If a new measurement completes before
the data is read, the data-ready signal becomes false.
The data-ready signal becomes true again when new
data is available in the data register.
The MAX1403 provides two methods of monitoring the
data-ready signal. INT provides a hardware solution
(active low when data is ready to be accessed), while
the DRDY bit in the COMM register provides a software
solution (active high).
Read data as soon as possible once data-ready
becomes true. This becomes increasingly important for
faster measurement rates. If the data read is delayed
significantly, a collision may result. A collision occurs
when a new measurement completes during a data-
register read operation. After a collision, information in
the data register is invalid. The failed read operation
must be completed even though the data is invalid.
Resetting the Interface
Reset the serial interface by clocking in 32 1s.
Resetting the interface does not affect the internal reg-
isters.
If continuous data output mode is in use, clock in eight
0s followed by 32 1s. More than 32 1s may be clocked
in, since a leading 0 is used as the start bit for all oper-
ations.
Continuous Data Output Mode
When scanning the input channels (SCAN = 1), the ser-
ial interface allows the data register to be read repeat-
edly without requiring a write to the COMM register.
The initial COMM write (01111000) is followed by 24
clocks (DIN = high) to read the 24-bit data register.
Once the data register has been read, it can be read
again after the next conversion by writing another 24
clocks (DIN = high). Terminate the continuous data out-
put mode by writing to the COMM register with any
valid access.
Modulator Data Output (MDOUT = 1)
Single-bit, raw modulator data is available at DOUT for
custom filtering when MDOUT = 1. INT provides a mod-
ulator clock for data synchronization. Data is valid on
the falling edge of INT. Write operations can still be
performed; however, read operations are disabled.
After MDOUT is returned to 0, valid data is accessed
by the normal serial-interface read operation.
On-Chip Registers
Communications Register
0/DRDY: (Default = 0) Data Ready Bit. On a write, this
bit must be reset to 0 to signal the start of the Com-
munications Register data word. On a read, a 1 in this
location (0/DRDY) signifies that valid data is available in
the data register. This bit is reset after the data register
is read or, if data is not read, 0/DRDY will go low at the
end of the next measurement.
RS2, RS1, RS0: (Default = 0, 0, 0) Register Select
Bits. These bits select the register to be accessed
(Table 1).
R/W: (Default = 0) Read/Write Bit. When set high, the
selected register is read; when R/W = 0, the selected
register is written.
RESET: (Default = 0) Software Reset Bit. Setting this
bit high causes the part to be reset to its default power-
up condition (RESET = 0).
STDBY: (Default = 0) Standby Power-Down Bit. Setting
the STDBY bit places the part in “standby” condition,
shutting down everything except the serial interface
and the CLK oscillator.
FSYNC: (Default = 0) Filter Sync Bit. When FSYNC = 0,
conversions are automatically performed at a data rate
determined by CLK, FS1, FS0, MF1, and MF0 bits.
When FSYNC = 1, the digital filter and analog modulator
First Bit (MSB)
(LSB)
FUNCTION
0
STDBY
0
RESET
0
Name
FSYNC
0
REGISTER SELECT BITS
RS0
0
RS1
0
DATA
RDY
Defaults
RS2
0
R/W
0/DRDY
Communications Register
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相關代理商/技術參數(shù)
參數(shù)描述
MAX1403EVL11 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX1403 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX1403EVSYSTEM 制造商:Maxim Integrated Products 功能描述:EVALUATION SYSTEM FOR THE MAX1403 - Boxed Product (Development Kits)
MAX1406C/D 功能描述:RS-232接口集成電路 RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝:
MAX1406CAE 功能描述:RS-232接口集成電路 RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝:
MAX1406CAE+ 功能描述:RS-232接口集成電路 15kV ESD-Protected 230kbps RS-232 LD/Rc RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝:
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