參數(shù)資料
型號(hào)： MAX1358BETL+W
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 50/71頁(yè)
文件大?。?/td> 0K
描述： DAS 16BIT DUAL 10:1 40-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 16 b
采樣率（每秒）： 21.94k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-TQFN-EP（6x6）
包裝： 托盤
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
54
______________________________________________________________________________________
MSB
LSB
UP4S
UP3S
UP2S
UP1S
X
UPIO_SPI Register (Power-On State: 0000 XXXX)
CS
WRITE TO DAS TO ENABLE SPI MODE
WRITE THROUGH DAS TO UPIO DEVICE
NORMAL WRITE TO DAS
SCLK
DIN
DN
DN-1 DN-2 DN-3
D3
D2
D1
D0
EN
EN-1 EN-2 EN-3
X
EN
EN-1 EN-2 EN-3
X
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
E3
E2
E1
E0
E3
E2
E1
E0
UPIO4
SET BY UPIO4_CTRL REGISTER
UPIO3
SET BY UPIO3_CTRL REGISTER
UPIO2
SET BY UPIO2_CTRL REGISTER
UPIO1
SET BY UPIO1_CTRL REGISTER
Figure 18. SPI Pass-Through Timing Diagram
The UPIO_SPI pass-through control register bits map
the serial interface signals to the UPIO pins, allowing
the DAS to drive other devices at CPOUT or DVDD volt-
age levels, depending on the SV_ bit setting found in
the UPIO_CTRL register. Individual bits are provided to
set only the desired UPIO inputs to the SPI pass-
through mode. This mode becomes active when
CS is
driven high to complete the write to this register, and
remains active as long as
CS stays high (i.e., multiple
pass-through writes are possible). The SPI pass-
through mode is deactivated immediately when
CS is
pulled low for the next DAS write.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the
CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 18 for an SPI pass-through timing diagram.
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted
CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
through mode is active, and is high (near DVDD or
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
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