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參數資料
| 型號： | MAX1358BETL+TW |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 28/71頁 |
| 文件大小： | 0K |
| 描述： | DAS 16BIT DUAL 10:1 40-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 數據采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數據接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
34
______________________________________________________________________________________
Single-Pole/Double-Throw (SPDT) Switches
The MAX1358B provides two uncommitted SPDT switch-
es. Each switch has a typical 35
Ω on-resistance. Control
the switches through the SW_CTRL register, the PWM
output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
Pulse-Width Modulator (PWM)
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most Cs have
built-in PWM functions, the MAX1358B PWM is more
flexible by allowing the UPIO outputs to be driven to
DVDD or regulated CPOUT logic-high voltage levels.
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is avail-
able independent of C power state. The FLL is typical-
Serial Interface
The MAX1358B features a 4-wire serial interface con-
sisting of a chip select (
CS), serial clock (SCLK), data
in (DIN), and data out (DOUT).
CS must be low to allow
data to be clocked into or out of the device. DOUT is
high impedance while
CS is high. The data is clocked
in at DIN on the rising edge of SCLK. Data is clocked
out at DOUT on the falling edge of SCLK. The serial
interface is compatible with SPI modes CPOL = 0,
CPHA = 0 and CPOL = 1, CPHA = 1. A write operation
to the MAX1358B takes effect on the last rising edge of
SCLK. If
CS goes high before the complete transfer, the
write is ignored. Every data transfer is initiated by the
command byte. The command byte consists of a start
bit (MSB), R/
W bit, and 6 address bits. The start bit
must be 1 to perform data transfers to the device.
Zeros clocked in are ignored. For SPI pass-through
mode, see the
UPIO_SPI Register section. An address
byte identifies each register. Table 4 shows the com-
plete register address map for this family of DAS.
Figures 14, 15, and 16 provide timing diagrams for
read and write commands.
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