- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9833 > MAX13433EESD+T (Maxim Integrated Products)TXRX RS-485 16MBPS FULL 14SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX13433EESD+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 5/20闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | TXRX RS-485 16MBPS FULL 14SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 椤炲瀷锛� | 鏀剁櫦(f膩)鍣� |
| 椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� | 1/1 |
| 瑕�(gu墨)绋嬶細 | RS485 |
| 闆绘簮闆诲锛� | 3 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)鐣�(d膩ng)鍓嶇5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)
RS-485 Transceivers with Low-Voltage
Logic Interface
PIN
MAX13432E/MAX13433E
SO
TDFN
NAME
FUNCTION
11
VL
VL Input Logic Supply Voltage. Bypass VL with a 0.1F ceramic capacitor located as
close as possible to the input.
22
RO
Receiver Output. When RE is low and if (A - B)
鈮� -50mV, RO is high; if (A - B) 鈮� -200mV,
RO is low.
33
DE
Driver Output Enable. Drive DE high to enable driver outputs. These outputs are high
impedance when DE is low. Drive RE high and DE low to enter low-power shutdown
mode. DE is a hot-swap input (see the Hot-Swap Capability section for details.)
44
RE
Active-Low Receiver Output Enable. Drive RE low to enable RO; RO is high impedance
when RE is high. Drive RE high and DE low to enter low-power shutdown mode. RE is a
hot-swap input (see the Hot-Swap Capability section for details.)
55
DI
Driver Input. With DE high, a low on DI forces noninverting output low and inverting output
high. Similarly, a high on DI forces noninverting output high and inverting output low.
6
GND
Ground
7, 13
N.C.
No Connection. Not internally connected. N.C. can be connected to GND.
8
GND
Ground
9
Y
Noninverting Driver Output
10
Z
Inverting Driver Output
11
B
Inverting Receiver Input
12
A
Noninverting Receiver Input
14
VCC
VCC Input Supply Voltage. Bypass VCC with a 1F ceramic capacitor located as close
as possible to the input for full ESD protection. If full ESD protection is not required,
bypass VCC with a 0.1F ceramic capacitor.
鈥�
EP
Exposed Pad (TDFN Only). Connect EP to GND.
Pin Description (continued)
MAX13430E鈥揗AX13433E
Maxim Integrated
13
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| GTC030-20-18P | CONN RCPT 9POS PANEL MNT W/PINS |
| MS3100F24-6S | CONN RCPT 8POS WALL MNT W/SCKT |
| MS3456W14S-7P | CONN PLUG 3POS STRAIGHT W/PINS |
| MAX13411EESA+T | IC TXRX RS-485 LDO/CTRL 8-SOIC |
| MS27656E13B22P | CONN RCPT 22POS WALL MNT W/PINS |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX13433EETD+ | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:LINE TRNSCVR 1TR 1TX 1RX 14TDFN EP - Rail/Tube |
| MAX13433EETD+T | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC Txrx RS-485 16Mbps Full RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MAX1343BETX | 鍔熻兘鎻忚堪:ADC / DAC澶氶€氶亾 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�:8 bit 鎺ュ彛椤炲瀷:SPI 闆诲鍙冭€�: 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-40 |
| MAX1343BETX+ | 鍔熻兘鎻忚堪:ADC / DAC澶氶€氶亾 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�:8 bit 鎺ュ彛椤炲瀷:SPI 闆诲鍙冭€�: 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-40 |
| MAX1343BETX+T | 鍔熻兘鎻忚堪:ADC / DAC澶氶€氶亾 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�:8 bit 鎺ュ彛椤炲瀷:SPI 闆诲鍙冭€�: 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-40 |
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