參數(shù)資料
型號(hào)： MAX1340BETX+T
廠商： Maxim Integrated Products
文件頁數(shù)： 4/39頁
文件大?。?/td> 0K
描述： IC ADC/DAC 12BIT W/FIFO 36WQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： ADC，DAC
分辨率（位）： 12 b
采樣率（每秒）： 225k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-TQFN 裸露焊盤（6x6）
包裝： 帶卷 (TR)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
12
______________________________________________________________________________________
Pin Description
MAX1340
MAX1342
MAX1346
MAX1348
NAME
FUNCTION
1, 2, 16–19,
24, 25
16–19
1, 2, 16–19,
24, 25, 31,
34
16–19, 31,
34
D.C.
Do Not Connect. Do not connect to this pin.
3
333
EOC
Active-Low End-of-Conversion Output. Data is valid after the
falling edge of
EOC.
4
444
DVDD
Digital Positive Power Input. Bypass DVDD to DGND with a
0.1F capacitor.
5
DGND
Digital Ground. Connect DGND to AGND.
6
DOUT
Serial Data Output. Data is clocked out on the falling edge of
the SCLK clock in clock modes 00, 01, and 10. Data is
clocked out on the rising edge of the SCLK clock in clock
mode 11. High impedance when
CS is high.
7
SCLK
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See Table 4 for
details on programming the clock mode.
8
888
DIN
Serial Data Input. DIN data is latched into the serial interface
on the falling edge of SCLK.
9–12
OUT0–
OUT3
DAC Outputs
13
AVDD
Positive Analog Power Input. Bypass AVDD to AGND with a
0.1F capacitor.
14
AGND
Analog Ground
15, 23, 32,
33
15, 23, 32,
33
15, 23, 32,
33
15, 23, 32,
33
N.C.
No Connection. Not internally connected.
20
LDAC
Active-Low Load DAC.
LDAC is an asynchronous active-low
input that updates the DAC outputs. Drive
LDAC low to make
the DAC registers transparent.
21
CS
Active-Low Chip-Select Input. When
CS is low, the serial
interface is enabled. When
CS is high, DOUT is high
impedance.
22
RES_SEL
Reset Select. Selects DAC wake-up mode. Set RES_SEL low
to wake up the DAC outputs with a 100k
resistor to GND or
set RES_SEL high to wake up the DAC outputs with a 100k
resistor to VREF. Set RES_SEL high to power up the DAC input
register to FFFh. Set RES_SEL low to power up the DAC input
register to 000h.
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