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參數(shù)資料
| 型號： | MAX132EWG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT SERIAL 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 100 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，雙極 |
MAX132
±18-Bit ADC with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602k
, CINT = 0.0047F, CREF = 0.1F,
fCLK = 32,768Hz, 60Hz mode, TA = TMIN to TMAX, unless otherwise noted.)
INTERFACE TIMING
(Test Circuit of Figure 1, Figure 2, V+ = 5V, V- = -5V, DGND = AGND = 0V, TA = +25°C, unless otherwise noted.) (Note 3)
Note 1: ±18-bit accuracy achieved by averaging multiple conversions.
Note 2: Maximum deviation from best straight-line fit.
Note 3: Guaranteed by design, not tested.
Note 4: Difference in reading for equal positive and negative inputs near full scale.
DOUT, IOUT = -100A
DOUT, IOUT = -1mA
CS, DIN, SCLK, and DOUT when three-stated
Referred to DGND, 4.5V
≤ V+ ≤ 5.5V, CS, DIN, SCLK
EOC, P0–P3, IOUT = -100A
DOUT, IOUT = 1.6mA
EOC, P0–P3, IOUT = 100A
Referred to DGND, 4.5V
≤ V+ ≤ 5.5V, CS, DIN, SCLK
CONDITIONS
4.0
4.5
3.5
4.3
pF
5
CIN
Input Capacitance
nA
±10
±500
IIN
Input Current
V
0.8
VIL
Input Low
V
4.0
4.7
VOH
Output High
0.1
0.4
V
0.1
0.4
VOL
Output Low
V
2.4
VIH
Input High
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
ns
500
t1
CS Lead Time
s
1
t5
CS High Pulse Width
ns
300
t4
SCLK Low Time
ns
400
t3
SCLK High Time
ns
400
t2
CS Lag Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
See Figure 4
See Figure 3
ns
0
t6
DIN to SCLK Setup Time
ns
320
t10
DOUT Disable Time to Three-State
ns
60
t9
Data Valid
ns
320
t8
DOUT Access Time from Three-State
ns
200
t7
DIN to SCLK Hold Time
ns
230
350
t12
Delay to P0–P3 Low
ns
230
350
t11
Delay to P0–P3 High
DIGITAL SECTION
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