參數(shù)資料
型號(hào): MAX1281BEUP+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 300KSPS 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 12
采樣率(每秒): 300k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 559mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)偽差分,單極;4 個(gè)偽差分,雙極
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
18
______________________________________________________________________________________
power consumption using the specified power-down
mode, with the internal reference and the maximum
clock speed. The clock speed in FASTPD or REDP
should be limited to 4.8MHz for the MAX1280/
MAX1281. FULLPD mode may provide increased power
savings in applications where the MAX1280/
MAX1281 are inactive for long periods of time, but
where intermittent bursts of high-speed conversions are
required.
Internal and External References
The MAX1280/MAX1281 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at REF for
both the MAX1280/MAX1281. The internally trimmed
1.22V reference is buffered with a gain of +2.05V/V.
Internal Reference
The MAX1280/MAX1281’s full-scale range with the inter-
nal reference is 2.5V for unipolar inputs and ±1.25V for
bipolar inputs. The internal reference voltage is
adjustable to ±100mV with the circuit of Figure 13.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the internal reference-
buffer amplifier. The REFADJ input impedance is typical-
ly 17k
. At REF, the DC input resistance is a minimum of
2.5
2.0
1.0
1.5
0.5
0
150
250
100
50
200
300
350
SAMPLING RATE (sps)
SUPPLY
CURRENT
(mA)
MAX1281, VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
REDP
FASTPD
NORMAL OPERATION
Figure 11. Average Supply Current vs. Sampling Rate (Using
REPD, FASTPD, and Normal Operation and Internal Reference)
Figure 12a. Full Power-Down Timing
RE FADJ
1.22V
0V
2.5mA
1.3mA OR 0.9mA
DIN
IVDD1 + IVDD2
REF
FULLPD
REDP
WAIT 2ms (10 x RC)
FULLPD
1
0 0
11
γ = RC = 17kx 0.01F
DUMMY CONVERSION
1
1 0
0 0
2.5V
2.5mA
0mA
2.5V
0V
Figure 12b. Reduced-Power/Fast Power-Down Timing
2.5V (ALWAYS ON)
2.5mA
DIN
IVDD1 + IVDD2
REF
REDPD
REDP
FASTPD
1
1 0
11
1 0
0 1
2.5mA
1.3mA
0.9mA
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