參數(shù)資料
型號(hào)： MAX1211
廠商： Maxim Integrated Products, Inc.
英文描述： 40Msps, 12-Bit ADC
中文描述： 12位、65Msps、中頻采樣ADC
文件頁(yè)數(shù)： 16/29頁(yè)
文件大?。?/td> 609K
代理商： MAX1211
M
40Msps, 12-Bit ADC
16
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
11
CLKTYP
Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OV
DD
or V
DD
to define the differential clock input.
12
–
15, 36
V
DD
Analog Power Input. Connect V
DD
to a 3.0V to 3.6V power supply. Bypass V
DD
to GND with a parallel
capacitor combination of
≥
2.2μF and 0.1μF. Connect all V
DD
pins to the same potential.
17, 34
OV
DD
Output Driver Power Input. Connect OV
DD
to a 1.7V to V
DD
power supply. Bypass OV
DD
to GND with a
parallel capacitor combination of
≥
2.2μF and 0.1μF.
18
DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range.
19
20
21
22
23
24
25
26
27
28
29
30
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I.C.
CMOS Digital Output, Bit 11 (MSB)
CMOS Digital Output, Bit 10
CMOS Digital Output, Bit 9
CMOS Digital Output, Bit 8
CMOS Digital Output, Bit 7
CMOS Digital Output, Bit 6
CMOS Digital Output, Bit 5
CMOS Digital Output, Bit 4
CMOS Digital Output, Bit 3
CMOS Digital Output, Bit 2
CMOS Digital Output, Bit 1
CMOS Digital Output, Bit 0 (LSB)
Internally Connected. Leave I.C. unconnected.
31, 32
33
DAV
Data Valid Output. The DAV is a single-ended version of the input clock that is compensated to correct
for any input clock duty-cycle variations. The MAX1211 evaluation kit (MAX1211EVKIT) utilizes DAV to
latch data (D0
–
D11) into external back-end digital circuitry.
37
PD
Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
38
REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive-divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥
0.1μF capacitor.
Reference Input. V
REFIN
= 2 x (V
REFP
- V
REFN
). Bypass REFIN to GND with a
≥
0.1μF capacitor.
Output Format Select Input. Connect G/
T
to GND for the two
’
s complement digital output format. Connect
G/
T
to OV
DD
or V
DD
for the Gray code digital output format.
39
REFIN
40
G/
T
—
EP
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified
performance.
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