參數(shù)資料
型號(hào)： MAX1204BMJP
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE
中文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝： 0.300 INCH, CERDIP-20
文件頁(yè)數(shù)： 18/24頁(yè)
文件大?。?/td> 170K
代理商： MAX1204BMJP
M
5V, 8-Channel, S erial, 10-Bit ADC
with 3V Digital Interfac e
18
______________________________________________________________________________________
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with external-
reference compensation in fast power-down, with one and
eight channels converted. The external 4.7μF compensa-
tion requires a 50μs wait after power-up. This circuit com-
bines fast multichannel conversion with the lowest power
consumption possible. Full power-down mode can
increase power savings in applications where the
MAX1204 is inactive for long periods of time, but where
intermittent bursts of high-speed conversions are required.
External and Internal Referenc es
The MAX1204 can be used with an internal or external
reference. An external reference can be connected
directly at the REF terminal or at the REFADJ pin.
An internal buffer is designed to provide 4.096V at REF
for the MAX1204. Its internally trimmed 2.44V reference
is buffered with a 1.68 nominal gain.
Internal Reference
The MAX1204’s full-scale range with internal reference is
4.096V with unipolar inputs and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the circuit of Figure 17.
External Reference
An external reference can be placed at either the input
(REFADJ ) or the output (REF) of the MAX1204’s internal
buffer amplifier. The REFADJ input impedance is typical-
ly 20k
. At REF, the input impedance is a minimum of
12k
for DC currents. During conversion, an external
reference at REF must deliver up to 350μA DC load cur-
rent and have an output impedance of 10
or less. If the
reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7μF capacitor.
Using the buffered REFADJ input makes buffering of
the external reference unnecessary. To use the direct
REF input, disable the internal buffer by tying REFADJ
to V
DD
. In power-down, the input bias current to
REFADJ can be as much as 25μA with REFADJ tied to
V
DD
. Pull REFADJ to GND to minimize the input bias
current in power-down.
T ransfer Func tion and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive integer LSB values. Output coding
is binary with 1 LSB = 4mV (4.096V/1024) for
unipolar operation and 1 LSB = 4mV [(4.096V/2 -
-4.096V/2)/1024] for bipolar operation.
Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence
1
0 0
DIN
REFADJ
REF
2.5V
0V
4V
0V
1
01
1
1
1
1
00
1
01
FULLPD
FASTPD
NOPD
FULLPD
FASTPD
2ms WAIT
COMPLETE CONVERSION SEQUENCE
t
BUFFEN
≈
15μs
τ
= RC = 20k
x C
REFADJ
(ZEROS)
CH1
CH7
(ZEROS)
Figure 12c. Additional I
DD
Shutdown Supply Current vs. V
IH
for Each Digital Input at a Logic 1
0
-60
10
5
TEMPERATURE (°C)
S
μ
A
100
25
20
15
-20
60
140
40
35
30
20
(V
DD
- V
IH
) = 1.95V
(V
DD
- V
IH
) = 2.55V
(V
DD
- V
IH
) = 2.25V
相關(guān)PDF資料
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