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| 型號： | MAX1204BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | 0.300 INCH, CERDIP-20 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MAX1204BMJP |
M
5V, 8-Channel, S erial, 10-Bit ADC
with 3V Digital Interfac e
______________________________________________________________________________________
17
Hardware Power-Down
The
SHDN
pin places the converter into full
power-down mode. Unlike the software power-down
modes, conversion is not completed; it stops coinci-
dentally with
SHDN
being brought low. There is no
power-up delay if an external reference, which is not
shut down, is used.
SHDN
also selects internal or
external reference compensation (Table 7).
Power-Down S equenc ing
The MAX1204’s automatic power-down modes can
save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1204’s power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01μF bypass
capacitor at REFADJ forms an RC filter with the internal
20k
reference resistor, with a 0.2ms time constant. To
achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
When exiting FULLPD, waiting this 2ms in FASTPD mode
(instead of just exiting FULLPD mode and returning to nor-
mal operating mode) reduces power consumption by a
factor of 10 or more (Figure 13).
Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)
FULL
POWER-DOWN
POWERED
UP
POWERED UP
DATA VALID
DATA VALID
INTERNAL CLOCK MODE
S X X X X X 1 0
S
0 0
X
X
X
X
X
S
MODE
DOUT
DIN
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
SETS FULL
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12a. Timing Diagram for Power-Down Modes (External Clock)
POWERED UP
FULL
POWER-
DOWN
POWERED
UP
POWERED UP
DATA VALID
(10 + 2 DATA BITS)
DATA VALID
(10 + 2 DATA BITS)
DATA
INVALID
EXTERNAL
EXTERNAL
INTERNAL
S X X X X X 1 1
S
0 1
X
X
X
X
X
X X X X X
S
1 1
FAST
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS FAST
POWER-DOWN
MODE
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